Commit eed1d9b6 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Andersson

arm64: dts: qcom: sdm845: Use RPMH_CE_CLK macro directly

In commit 3e482859 ("dts: qcom: sdm845: Add dt entries
to support crypto engine."), we decided to use the value indicated
by constant RPMH_CE_CLK rather than using it directly.

Now that the same RPMH clock value might be used for other
SoCs (in addition to sdm845), let's use the constant
RPMH_CE_CLK to make sure that this dtsi is compatible with the
other qcom ones.
Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: default avatarThara Gopinath <thara.gopinath@linaro.org>
Link: https://lore.kernel.org/r/20210519143700.27392-8-bhupesh.sharma@linaro.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 6880fa6c
...@@ -2311,7 +2311,7 @@ cryptobam: dma@1dc4000 { ...@@ -2311,7 +2311,7 @@ cryptobam: dma@1dc4000 {
compatible = "qcom,bam-v1.7.0"; compatible = "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>; reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rpmhcc 15>; clocks = <&rpmhcc RPMH_CE_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
#dma-cells = <1>; #dma-cells = <1>;
qcom,ee = <0>; qcom,ee = <0>;
...@@ -2327,7 +2327,7 @@ crypto: crypto@1dfa000 { ...@@ -2327,7 +2327,7 @@ crypto: crypto@1dfa000 {
reg = <0 0x01dfa000 0 0x6000>; reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>, clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>,
<&rpmhcc 15>; <&rpmhcc RPMH_CE_CLK>;
clock-names = "iface", "bus", "core"; clock-names = "iface", "bus", "core";
dmas = <&cryptobam 6>, <&cryptobam 7>; dmas = <&cryptobam 6>, <&cryptobam 7>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
......
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