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Commit f633ebe4 authored by Tudor Ambarus's avatar Tudor Ambarus
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mtd: spi-nor: Use dev_dbg insted of dev_err for low level info 

What most users care about is "my dev is not working properly".
All low level information should be discovered when activating
the debug traces.

Keep error messages just for the following cases:
- when the SR/FSR report program or erase fails, or attempts of
  modifying a protected sector,
- when the JEDEC ID is not recognized,
- when the resume() call fails,
- when the spi_nor_check() fails.
Suggested-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 3d63ee5d
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Inline Side-by-side
Showing with 21 additions and 21 deletions
drivers/mtd/spi-nor/spi-nor.c
View file @ f633ebe4
...@@ -451,7 +451,7 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) ...@@ -451,7 +451,7 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
} }
if (ret) if (ret)
dev_err(nor->dev, "error %d reading SR\n", ret); dev_dbg(nor->dev, "error %d reading SR\n", ret);
return ret; return ret;
} }
...@@ -482,7 +482,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) ...@@ -482,7 +482,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
} }
if (ret) if (ret)
dev_err(nor->dev, "error %d reading FSR\n", ret); dev_dbg(nor->dev, "error %d reading FSR\n", ret);
return ret; return ret;
} }
...@@ -513,7 +513,7 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) ...@@ -513,7 +513,7 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
} }
if (ret) if (ret)
dev_err(nor->dev, "error %d reading CR\n", ret); dev_dbg(nor->dev, "error %d reading CR\n", ret);
return ret; return ret;
} }
...@@ -647,7 +647,7 @@ static int s3an_sr_ready(struct spi_nor *nor) ...@@ -647,7 +647,7 @@ static int s3an_sr_ready(struct spi_nor *nor)
ret = spi_nor_xread_sr(nor, nor->bouncebuf); ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret) { if (ret) {
dev_err(nor->dev, "error %d reading XRDSR\n", ret); dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
return ret; return ret;
} }
...@@ -770,7 +770,7 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, ...@@ -770,7 +770,7 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
cond_resched(); cond_resched();
} }
dev_err(nor->dev, "flash operation timed out\n"); dev_dbg(nor->dev, "flash operation timed out\n");
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -807,7 +807,7 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) ...@@ -807,7 +807,7 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr)
} }
if (ret) { if (ret) {
dev_err(nor->dev, dev_dbg(nor->dev,
"error while writing configuration register\n"); "error while writing configuration register\n");
return -EINVAL; return -EINVAL;
} }
...@@ -1771,7 +1771,7 @@ static int macronix_quad_enable(struct spi_nor *nor) ...@@ -1771,7 +1771,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
return ret; return ret;
if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) { if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
dev_err(nor->dev, "Macronix Quad bit not set\n"); dev_dbg(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL; return -EINVAL;
} }
...@@ -1819,7 +1819,7 @@ static int spansion_quad_enable(struct spi_nor *nor) ...@@ -1819,7 +1819,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
return ret; return ret;
if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) { if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n"); dev_dbg(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL; return -EINVAL;
} }
...@@ -1897,7 +1897,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) ...@@ -1897,7 +1897,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return ret; return ret;
if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) { if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n"); dev_dbg(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL; return -EINVAL;
} }
...@@ -1935,7 +1935,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ...@@ -1935,7 +1935,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
ret = spi_nor_write_sr2(nor, sr2); ret = spi_nor_write_sr2(nor, sr2);
if (ret) { if (ret) {
dev_err(nor->dev, "error while writing status register 2\n"); dev_dbg(nor->dev, "error while writing status register 2\n");
return ret; return ret;
} }
...@@ -1949,7 +1949,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ...@@ -1949,7 +1949,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
return ret; return ret;
if (!(*sr2 & SR2_QUAD_EN_BIT7)) { if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
dev_err(nor->dev, "SR2 Quad bit not set\n"); dev_dbg(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL; return -EINVAL;
} }
...@@ -1978,7 +1978,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) ...@@ -1978,7 +1978,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
ret = spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); ret = spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) { if (ret) {
dev_err(nor->dev, "write to status register failed\n"); dev_dbg(nor->dev, "write to status register failed\n");
return ret; return ret;
} }
...@@ -2525,7 +2525,7 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) ...@@ -2525,7 +2525,7 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
SPI_NOR_MAX_ID_LEN); SPI_NOR_MAX_ID_LEN);
} }
if (tmp) { if (tmp) {
dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp); dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp); return ERR_PTR(tmp);
} }
...@@ -2740,7 +2740,7 @@ static int s3an_nor_setup(struct spi_nor *nor, ...@@ -2740,7 +2740,7 @@ static int s3an_nor_setup(struct spi_nor *nor,
ret = spi_nor_xread_sr(nor, nor->bouncebuf); ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret) { if (ret) {
dev_err(nor->dev, "error %d reading XRDSR\n", ret); dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
return ret; return ret;
} }
...@@ -4102,7 +4102,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, ...@@ -4102,7 +4102,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
err = spi_nor_read_sfdp(nor, sizeof(header), err = spi_nor_read_sfdp(nor, sizeof(header),
psize, param_headers); psize, param_headers);
if (err < 0) { if (err < 0) {
dev_err(dev, "failed to read SFDP parameter headers\n"); dev_dbg(dev, "failed to read SFDP parameter headers\n");
goto exit; goto exit;
} }
} }
...@@ -4349,7 +4349,7 @@ static int spi_nor_default_setup(struct spi_nor *nor, ...@@ -4349,7 +4349,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,
/* Select the (Fast) Read command. */ /* Select the (Fast) Read command. */
err = spi_nor_select_read(nor, shared_mask); err = spi_nor_select_read(nor, shared_mask);
if (err) { if (err) {
dev_err(nor->dev, dev_dbg(nor->dev,
"can't select read settings supported by both the SPI controller and memory.\n"); "can't select read settings supported by both the SPI controller and memory.\n");
return err; return err;
} }
...@@ -4357,7 +4357,7 @@ static int spi_nor_default_setup(struct spi_nor *nor, ...@@ -4357,7 +4357,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,
/* Select the Page Program command. */ /* Select the Page Program command. */
err = spi_nor_select_pp(nor, shared_mask); err = spi_nor_select_pp(nor, shared_mask);
if (err) { if (err) {
dev_err(nor->dev, dev_dbg(nor->dev,
"can't select write settings supported by both the SPI controller and memory.\n"); "can't select write settings supported by both the SPI controller and memory.\n");
return err; return err;
} }
...@@ -4365,7 +4365,7 @@ static int spi_nor_default_setup(struct spi_nor *nor, ...@@ -4365,7 +4365,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,
/* Select the Sector Erase command. */ /* Select the Sector Erase command. */
err = spi_nor_select_erase(nor); err = spi_nor_select_erase(nor);
if (err) { if (err) {
dev_err(nor->dev, dev_dbg(nor->dev,
"can't select erase settings supported by both the SPI controller and memory.\n"); "can't select erase settings supported by both the SPI controller and memory.\n");
return err; return err;
} }
...@@ -4686,7 +4686,7 @@ static int spi_nor_init(struct spi_nor *nor) ...@@ -4686,7 +4686,7 @@ static int spi_nor_init(struct spi_nor *nor)
err = nor->clear_sr_bp(nor); err = nor->clear_sr_bp(nor);
if (err) { if (err) {
dev_err(nor->dev, dev_dbg(nor->dev,
"fail to clear block protection bits\n"); "fail to clear block protection bits\n");
return err; return err;
} }
...@@ -4694,7 +4694,7 @@ static int spi_nor_init(struct spi_nor *nor) ...@@ -4694,7 +4694,7 @@ static int spi_nor_init(struct spi_nor *nor)
err = spi_nor_quad_enable(nor); err = spi_nor_quad_enable(nor);
if (err) { if (err) {
dev_err(nor->dev, "quad mode not supported\n"); dev_dbg(nor->dev, "quad mode not supported\n");
return err; return err;
} }
...@@ -4762,7 +4762,7 @@ static int spi_nor_set_addr_width(struct spi_nor *nor) ...@@ -4762,7 +4762,7 @@ static int spi_nor_set_addr_width(struct spi_nor *nor)
} }
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
dev_err(nor->dev, "address width is too large: %u\n", dev_dbg(nor->dev, "address width is too large: %u\n",
nor->addr_width); nor->addr_width);
return -EINVAL; return -EINVAL;
} }
......
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