Commit fd962781 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Geert Uytterhoeven

riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT

RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance
helpers, which are built into the kernel unconditionally.
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.deSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1531309a
...@@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT ...@@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT
config RISCV_NONSTANDARD_CACHE_OPS config RISCV_NONSTANDARD_CACHE_OPS
bool bool
depends on RISCV_DMA_NONCOHERENT
help help
This enables function pointer support for non-standard noncoherent This enables function pointer support for non-standard noncoherent
systems to handle cache management. systems to handle cache management.
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...@@ -3,7 +3,7 @@ menu "Cache Drivers" ...@@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller" bool "Andes Technology AX45MP L2 Cache controller"
depends on RISCV_DMA_NONCOHERENT depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS select RISCV_NONSTANDARD_CACHE_OPS
help help
Support for the L2 cache controller on Andes Technology AX45MP platforms. Support for the L2 cache controller on Andes Technology AX45MP platforms.
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