- 31 May, 2024 37 commits
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Jani Nikula authored
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also fix comment in intel_pci_config.h (Ilpo) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0e344a72e9be596ac2b8b55a26fd674a96f03cdc.1717075103.git.jani.nikula@intel.com
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Jani Nikula authored
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Acked-by:
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Jani Nikula authored
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also change Documentation/gpu/i915.rst (Andi) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by:
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Jani Nikula authored
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Reviewed-by:
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Jani Nikula authored
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
With the refactoring in the file, some excessive includes were left behind and are now unnecessary. Remove. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-2-jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
With the register header refactoring, some of the includes of i915_reg.h have become unnecessary. Remove. Reviewed-by:
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Jani Nikula authored
The intermediate macros are unused. Remove them. Reviewed-by:
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Jani Nikula authored
Move the macros where they belong. Reviewed-by:
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Jani Nikula authored
Follow the recommended style for grouping register macros. Reviewed-by:
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Jani Nikula authored
The intermediate macros are no longer needed. Reviewed-by:
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Jani Nikula authored
Use the proper helpers for DP AUX CH CTL registers, instead of reinventing the wheels. Reviewed-by:
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Ville Syrjälä authored
Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(), with its 32bit maths, is currently limited to a few milliseconds. I want bigger numbers in DSB selftests, so switch over to 64bit maths. Signed-off-by:
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Ville Syrjälä authored
I want to use intel_crtc_scanline_offset() in intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset() a bit to avoid a forward declaration. Signed-off-by:
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Ville Syrjälä authored
Currently intel_crtc_scanline_offset() is careful to always return a positive offset. That is not actually necessary as long as we take care of negative values when applying the offset in __intel_get_crtc_scanline(). This simplifies intel_crtc_scanline_offset(), and makes the scanline_offfset arithmetic more symmetric between the forward (__intel_get_crtc_scanline()) and reverse (intel_crtc_scanline_to_hw()) directions. Signed-off-by:
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Ville Syrjälä authored
We have several copies of code calculating the hardware's idea of vtotal. Pull that to a helper, similar to intel_mode_vblank_{start,end}(). Signed-off-by: -
Ville Syrjälä authored
Extract intel_mode_vblank_end() in the same vein as intel_mode_vblank_start(). While we have only one use of this it seems nicer to unify the approach. Signed-off-by:
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Ville Syrjälä authored
Replace a few hand rolled copies of intel_mode_vblank_start() with the real thing. Signed-off-by:
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Ville Syrjälä authored
skl_ddb_add_affected_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. The wm counterpart (skl_wm_add_affected_planes()) already does things in the proper way. Signed-off-by:
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Ville Syrjälä authored
icl_check_nv12_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. Signed-off-by:
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Ville Syrjälä authored
Various parts of the cdclk code need access the full atomic state. Currently it's being dug out via the cdclk_state->base.state pointer, which is not great as that pointer isn't always valid. Instead plumb the full atomic state from the top so that it's clear that it is in fact valid. Signed-off-by:
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Jani Nikula authored
Add an info message about which display device was probed. Reviewed-by:
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Jani Nikula authored
Add support for subplatforms. This is similar to what the xe driver is doing. The subplatform is an enum and it's exclusive, i.e. only one subplatform can match, and it completely identifies the platform and subplatform. This is different from i915 core, and is notable in the handling of ULT/ULX and RPL/RPL-U. Reviewed-by:
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Jani Nikula authored
Add enum intel_display_platform and add that and name to all platform descriptors. Reviewed-by:
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Jani Nikula authored
We'll need to identify all platforms, including the ones that have display defined by GMD ID. Add MTL and LNL. Their display info will still be probed via GMD ID. Reviewed-by:
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Jani Nikula authored
Although not supported by i915 core, the display code needs to know the LNL PCI IDs. Long term, xe and i915 should probably share the file defining PCI IDs. Reviewed-by:
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Jani Nikula authored
We'll need to start identifying the platforms independently in display code in order to break free from the i915 and xe IS_<PLATFORM>() macros. This is fairly straightforward, as we already identify most platforms by PCI ID in display probe anyway. As the first step, add platform descriptors with pointers to display info. We'll have more platforms than display info, so minimize duplication: - Add separate skl/kbl/cfl/cml descriptors while they share the display info. - Add separate jsl/ehl descriptors while they share the display info. Identify ADL-P (and derivatives) and DG2 descriptors by their names even though their display info is Xe LPD or HPD. Reviewed-by:
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Jani Nikula authored
Add a name to the display ip version structure, and pass that around instead of a triplet of u16's. Reviewed-by:
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Jani Nikula authored
The main change here is that the check for platforms without display is now also done for GMD ID based platforms. However, without matches, the end result is the same. Reviewed-by:
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Jani Nikula authored
Return NULL for errors, and handle the no display case in one location. This will make subsequent changes easier. Reviewed-by:
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Jani Nikula authored
Copy the parameters earlier to make subsequent changes easier. Reviewed-by:
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Animesh Manna authored
For validation purpose add debugfs for LOBF. v1: Initial version. v2: Add aux-wake/less info along with lobf status. [Jouni] Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-7-animesh.manna@intel.com
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Animesh Manna authored
Set the Link Off Between Frames Enable bit in ALPM_CTL register. Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise after cmmr feature enablement. Will add enabling sequence in a separate patch. v1: Initial version. v2: Condition check modified in alpm_configure(). [Jouni] Reviewed-by:
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Animesh Manna authored
Link Off Between Active Frames, is a new feature for eDP that allows the panel to go to lower power state after transmission of data. This is a feature on top of ALPM, AS SDP. Add compute config during atomic-check phase. v1: RFC version. v2: Add separate flag for auxless-alpm. [Jani] v3: - intel_dp->lobf_supported replaced with crtc_state->has_lobf. [Jouni] - Add DISPLAY_VER() check. [Jouni] - Modify function name of get_aux_less_status. [Jani] v4: Add enum alpm_mode to hold the aux-wake/less capability. v5: Add alpm_dpcd to intel_dp and use aux_wake_supported()/ aux_less_wake_supported() instead of enum alpm_mode. [Jouni] Reviewed-by:
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Jouni Högander authored
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Acked-by:
Maxime Ripard <mripard@kernel.org> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Animesh Manna authored
Move ALPM feature related code as it will be used for non-psr panel also thorugh LOBF feature. v1: Initial version. v2: Correct ordering in makefile. [Jani] Reviewed-by:
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Animesh Manna authored
ALPM can be enabled for non psr panel and currenly aplm-params are encapsulated under intel_psr struct, so moving out to intel_dp struct. Reviewed-by:
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- 30 May, 2024 3 commits
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Luca Coelho authored
In intel_crtc_vblank_work(), we access uapi.event before grabbing the event_lock spinlock, but modify it inside the spinlock block. This causes some static analyzers to get confused and issue a warning. The uapi.event value is not protected by the event_lock, so we can safely move it out of the protected block to prevent false positives. Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528112901.476068-3-luciano.coelho@intel.com
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Luca Coelho authored
During static analysis, a concern was raised that we may access the dtd->dtd[] array out of bounds, because we are not checking whether the index we use is larger than the array. This should not be a problem as is, because the enumeration that is used for this index comes from "panel_type", which uses an enumeration with 4 items. But if this enumeration is ever changed, it can lead to hard-to-detect bugs, so better double-check it before using it as an index to the array. Signed-off-by:
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Mika Kahola authored
Currently, we may bump into pll mismatch errors during the state verification stage. This happens when we try to use fastset instead of full modeset. Hence, we would need to add a check for pipe configuration to ensure that the sw and the hw configuration will match. In case of hw and sw mismatch, we would need to disable fastset and use full modeset instead. v2: Fix C10 error on PLL comparison (BAT) Use memcmp instead of fixed loops for pll config comparison (Jani) Clean up and use intel_cx0pll_dump_hw_state() to dump pll information (Jani) Reviewed-by:Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com
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