- 03 Aug, 2017 14 commits
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Benjamin Herrenschmidt authored
No need to break those lines, they aren't that long Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Benjamin Herrenschmidt authored
It makes do_page_fault() more readable. No functional change. Signed-off-by:
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Benjamin Herrenschmidt authored
First, handle the normal retry failure in do_page_fault itself, since it's a simple return statement. That allows us to remove the "continue" special return code from mm_fault_error(). Once that's done, we can have an implementation much closer to x86 where we only call mm_fault_error() if VM_FAULT_ERROR is set and directly return. Signed-off-by:
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Benjamin Herrenschmidt authored
Instead of goto labels, instead call those functions and return. This gets us closer to x86 and allows us to shring do_page_fault() even more. The main difference with x86 is that those function return a value which we then return from do_page_fault(). That value is our return value from do_page_fault() which we use to generate kernel faults. Signed-off-by:
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Benjamin Herrenschmidt authored
We currently test for is_exec and DSISR_PROTFAULT but that doesn't make sense as this is the wrong error bit to test for an execute permission failure. In fact, we had code that would return early if we had an exec fault in kernel mode so I think that was just dead code anyway. Finally the location of that test is awkward and prevents further simplifications. So instead move that test into a helper along with the existing early test for kernel exec faults and out of range accesses, and put it all in a "bad_kernel_fault()" helper. While at it test the correct error bits. Signed-off-by:
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Benjamin Herrenschmidt authored
Now that we moved the exception state handling to a wrapper, we can just directly return rather than "goto bail" Signed-off-by:
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Benjamin Herrenschmidt authored
unclutters the main path Signed-off-by:
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Benjamin Herrenschmidt authored
A bad page fault is when the HW signals an error such as a bad copy/paste, an AMO error, or some other type of error that will not be fixed by updating the PTE. Use a helper page_fault_is_bad() to check for bad page faults thus removing the per-processor family open-coding in __do_page_fault() and trigger a SIGBUS rather than a SIGSEGV which is more appropriate. Signed-off-by:
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Benjamin Herrenschmidt authored
There's no point looking for the VMA etc.. when we already know we are going to fail. This adds some code to set "code" for the si_code but that will be gone in subsequent patches. Signed-off-by:
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Benjamin Herrenschmidt authored
Define a common page_fault_is_write() helper and use it Signed-off-by:
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Benjamin Herrenschmidt authored
This uses the newly defined constants for this rather than open-coded numbers. There is a side effect on 64-bit which is to pass through some of the new P9 bits which we didn't before. Signed-off-by:
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Benjamin Herrenschmidt authored
We test a number of bits from DSISR/SRR1 before deciding to call hash_page(). If any of these is set, we go directly to do_page_fault() as the bit indicate a fault that needs to be handled there (no hashing needed). This updates the current open-coded masks to use the new DSISR definitions. This *does* change the masks actually used in two ways: - We used to test various bits that were defined as "always 0" in the architecture and could be repurposed for something else. From now on, we just ignore such bits. - We were missing some new bits defined on P9 Signed-off-by:
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Benjamin Herrenschmidt authored
This updates the definitions for the various DSISR bits to match both some historical stuff and to match new bits on POWER9. In addition, we define some masks corresponding to the "bad" faults on Book3S, and some masks corresponding to the bits that match between DSISR and SRR1 for a DSI and an ISI. This comes with a small code update to change the definition of DSISR_PGDIRFAULT which becomes DSISR_PRTABLE_FAULT to match architecture 3.0B Signed-off-by:
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Benjamin Herrenschmidt authored
On legacy 6xx 32-bit procesors, we checked for the DABR match bit in DSISR from do_page_fault(), in the middle of a pile of ifdef's because all other CPU types do it in assembly prior to calling do_page_fault. Fix that. Signed-off-by:
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- 02 Aug, 2017 5 commits
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Benjamin Herrenschmidt authored
By filtering the relevant SRR1 bits in the assembly rather than in do_page_fault() itself, we avoid a conditional branch (since we already come from different path for data and instruction faults). This will allow more simplifications later Signed-off-by:
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Benjamin Herrenschmidt authored
This will allow simplifying the returns from do_page_fault Signed-off-by:
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Benjamin Herrenschmidt authored
We do that because it's used by THP pmd collapsing, so use instead a dedicated flush function. Signed-off-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
At the moment we have to rather sub-optimal flushing behaviours: - flush_tlb_mm() will flush the PWC which is unnecessary (for example when doing a fork) - A large unmap will call flush_tlb_pwc() multiple times causing us to perform that fairly expensive operation repeatedly. This happens often in batches of 3 on every new process. So we change flush_tlb_mm() to only flush the TLB, and we use the existing "need_flush_all" flag in struct mmu_gather to indicate that the PWC needs flushing. Unfortunately, flush_tlb_range() still needs to do a full flush for now as it's used by the THP collapsing. We will fix that later. Signed-off-by:
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Benjamin Herrenschmidt authored
The PWC flush only needs a single set call, just like the full (RIC=2) flush. This will allow us to get rid of the dedicated _tlbiel_pwc() Signed-off-by:
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- 01 Aug, 2017 3 commits
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Victor Aoqui authored
Replace the __this_cpu_read() with raw_cpu_read() in iommu_range_alloc(). Otherwise we get a warning about using __this_cpu_read() in preemptible code: BUG: using __this_cpu_read() in preemptible caller is iommu_range_alloc+0xa8/0x3d0 Preemption doesn't need to be disabled since according to the comment any CPU can safely use any IOMMU pool. Signed-off-by:
Victor Aoqui <victora@linux.vnet.ibm.com> Signed-off-by:
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Gautham R. Shenoy authored
Currently we use the stop-api provided by the firmware to program the SLW engine to restore the values of hypervisor resources that get lost on deeper idle states (such as winkle). Since the deep states were only used for CPU-Hotplug on POWER8 systems, we would program the LPCR to have the PECE1 bit since Hotplugged CPUs shouldn't be spuriously woken up by decrementer. On POWER9, some of the deep platform idle states such as stop4 can be used in cpuidle as well. In this case, we want the CPU in stop4 to be woken up by the decrementer when some timer on the CPU expires. In this patch, we program the stop-api for LPCR with PECE1 bit cleared only when we are offlining the CPU and set it back once the CPU is online. Signed-off-by:
Gautham R. Shenoy <ego@linux.vnet.ibm.com> Reviewed-by:
Nicholas Piggin <npiggin@gmail.com> Signed-off-by:
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Gautham R. Shenoy authored
The stop4 idle state on POWER9 is a deep idle state which loses hypervisor resources, but whose latency is low enough that it can be exposed via cpuidle. Until now, the deep idle states which lose hypervisor resources (eg: winkle) were only exposed via CPU-Hotplug. Hence currently on wakeup from such states, barring a few SPRs which need to be restored to their older value, rest of the SPRS are reinitialized to their values corresponding to that at boot time. When stop4 is used in the context of cpuidle, we want these additional SPRs to be restored to their older value, to ensure that the context on the CPU coming back from idle is same as it was before going idle. In this patch, we define a SPR save area in PACA (since we have used up the volatile register space in the stack) and on POWER9, we restore SPRN_PID, SPRN_LDBAR, SPRN_FSCR, SPRN_HFSCR, SPRN_MMCRA, SPRN_MMCR1, SPRN_MMCR2 to the values they had before entering stop. Signed-off-by:
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- 31 Jul, 2017 3 commits
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Rui Teng authored
The offset of hugepage block will not be 16G, if the expected page is more than one. Calculate the totol size instead of the hardcode value. Fixes: 4792adba ("powerpc: Don't use a 16G page if beyond mem= limits") Signed-off-by:
Rui Teng <rui.teng@linux.vnet.ibm.com> Tested-by:
Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by:
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Michael Ellerman authored
For debugging very early boot problems we have CONFIG_PPC_EARLY_DEBUG, which allows configuring the kernel such that it unconditionally writes to a particular type of console, regardless of whether that console exists or not. This is useful sometimes when the kernel crashes before it can even determine what platform it's on, and therefore what consoles exist. However if you boot a kernel built this way on a different platform, it will generally crash because it writes to a console that doesn't exist. A particularly nasty instance of this is if you enable the hypervisor console early debug, and then boot that kernel on bare metal. The result is that the kernel calls "the hypervisor" very early in boot, but the kernel *is* the hypervisor, so we jump to the system call handler and start executing all sorts of code that isn't ready to be run. This may lead to a machine check or check stop depending on how lucky you are. Luckily there is an easy way to avoid this particular case. We simply read the MSR before installing the hooks, and if we see MSR_HV is set then we are the hypervisor and we definitely should not use the hypervisor console. Signed-off-by: -
Michael Ellerman authored
Although pretty much everyone using powernv is running little endian, we should still test we can build for big endian. So add a powernv_be_defconfig, which is autogenerated by flipping the endian symbol in powernv_defconfig. Signed-off-by:
Cyril Bur <cyrilbur@gmail.com>
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- 25 Jul, 2017 4 commits
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Anju T Sudhakar authored
Add support to register Thread In-Memory Collection PMU counters. Patch adds thread IMC specific data structures, along with memory init functions and CPU hotplug support. Signed-off-by:
Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by:
Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by:
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Anju T Sudhakar authored
Add support to register Core In-Memory Collection PMU counters. Patch adds core IMC specific data structures, along with memory init functions and CPU hotplug support. Signed-off-by:
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Anju T Sudhakar authored
Add support to register Nest In-Memory Collection PMU counters. Patch adds a new device file called "imc-pmu.c" under powerpc/perf folder to contain all the device PMU functions. Device tree parser code added to parse the PMU events information and create sysfs event attributes for the PMU. Cpumask attribute added along with Cpu hotplug online/offline functions specific for nest PMU. A new state "CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE" added for the cpu hotplug callbacks. Error handle path frees the memory and unregisters the CPU hotplug callbacks. Signed-off-by:
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Madhavan Srinivasan authored
Code to create platform device for the In-Memory Collection (IMC) counters. Platform devices are created based on the IMC compatibility. New header file created to contain the data structures and macros needed for In-Memory Collection (IMC) counter pmu devices. The device tree for IMC counters starts at the node "imc-counters". This node contains all the IMC PMU nodes and event nodes for these IMC PMUs. Device probe() parses the device to locate three possible IMC device types (Nest/Core/Thread). Function then branch to parse each unit nodes to populate vital information such as device memory sizes, event nodes information, base address for reserve memory access (if any) and so on. Simple bare-minimum shutdown function added which only "stops" the engines. Signed-off-by:
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- 24 Jul, 2017 8 commits
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Madhavan Srinivasan authored
In-Memory Collection (IMC) counters are performance monitoring infrastructure. These counters need special sequence of SCOMs to init/start/stop which is handled by OPAL. And OPAL provides three APIs to init and control these IMC engines. OPAL API documentation: https://github.com/open-power/skiboot/blob/master/doc/opal-api/opal-imc-counters.rst Patch updates the kernel side powernv platform code to support the new OPAL APIs Signed-off-by:
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Aneesh Kumar K.V authored
We can use pfn_to_page() in realmode for other configs. Hence remove the CONFIG_FLATMEM ifdef. Fixes: 8e0861fa ("powerpc: Prepare to support kernel handling of IOMMU map/unmap") Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by:
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Geliang Tang authored
Use memdup_user() helper instead of open-coding to simplify the code. Signed-off-by:
Geliang Tang <geliangtang@gmail.com> Signed-off-by:
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Michael Ellerman authored
All cases initialise rv, and if they didn't that would be a bug. By dropping the initialisation we give the compiler the chance to catch those bugs for us. Signed-off-by: -
Geliang Tang authored
Use memdup_user_nul() helper instead of open-coding to simplify the code. Signed-off-by:
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Scott Wood authored
External IRQ0 (index 48) has the same capabilities as the other IRQ1-7 and is handled by the same register IPIC_SEPNR. When this register is not specified for "ack" in "ipic_info", you cannot configure this IRQ as IRQ_TYPE_EDGE_FALLING. This oversight was probably due to the non-contiguous hwirq numbering of IRQ0 in the IPIC. Signed-off-by:
Jurgen Schindele <schindele@nentec.de> [scottwood: Cleaned up commit message and posted as a proper patch] Signed-off-by:
Scott Wood <oss@buserror.net> Signed-off-by:
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Laurentiu Tudor authored
This allows building powerpc with the GENERIC_MSI_IRQ_DOMAIN Kconfig by enabling the asm-generic msi.h in Kbuild. Without this, there's a compilation error [1] because powerpc, as most arches, doesn't provide an asm/msi.h. [1] In file included from ./include/linux/kvm_host.h:20:0, from ./arch/powerpc/include/asm/kvm_ppc.h:30, from arch/powerpc/kernel/dbell.c:20: ./include/linux/msi.h:195:21: fatal error: asm/msi.h: No such file or directory Signed-off-by:Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by:
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Santosh Sivaraj authored
Check for validity of cpu before calling get_hard_smp_processor_id(). Found with coverity. Signed-off-by:
Santosh Sivaraj <santosh@fossix.org> Signed-off-by:
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- 23 Jul, 2017 3 commits
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Linus Torvalds authored
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Linus Torvalds authored
This adds a perl script to actually parse the MAINTAINERS file, clean up some whitespace in it, warn about errors in it, and then properly sort the end result. My perl-fu is atrocious, so the script has basically been created by randomly putting various characters in a pile, mixing them around, and then looking it the end result does anything interesting when used as a perl script. Signed-off-by:Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
Prepping for scripting the MAINTAINERS file cleanup (and possible split) showed a couple of cases where the headers for a couple of entries were bogus. There's a few different kinds of bogosities: - the X-GENE SOC EDAC case was confused and split over two lines - there were four entries for "GREYBUS PROTOCOLS DRIVERS" that were all different things. - the NOKIA N900 CAMERA SUPPORT" was duplicated all of which were more obvious when you started doing associative arrays in perl to track these things by the header (so that we can alphabetize this thing properly, and so that we might split it up by the data too). Cc: Joe Perches <joe@perches.com> Signed-off-by:
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