- 11 Oct, 2013 40 commits
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Kevin Hao authored
We already got the value of current_thread_info and ti_flags and store them into r9 and r4 respectively before jumping to resume_kernel. So there is no reason to reload them again. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Bartlomiej Zolnierkiewicz authored
__initdata tag should be placed between the variable name and equal sign for the variable to be placed in the intended .init.data section. Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
__initdata tag should be placed between the variable name and equal sign for the variable to be placed in the intended .init.data section. Signed-off-by:
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Scott Wood authored
Otherwise, we get a debug traceback due to the use of smp_processor_id() (or get_paca()) inside hard_smp_processor_id(). mpic_host_map() is just looking for a default CPU, so it doesn't matter if we migrate after getting the CPU ID. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Anton Blanchard authored
Temporarily work around an ICE we are seeing while building in little endian mode: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57134Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Anton Blanchard authored
POWER7 takes alignment exceptions on some unaligned addresses, so disable HAVE_EFFICIENT_UNALIGNED_ACCESS. This fixes an early boot issue in the printk code. Signed-off-by:
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Ian Munsie authored
This patch allows the kbuild system to successfully compile a kernel for the little endian PowerPC64 architecture. A subsequent patch will add the CONFIG_CPU_LITTLE_ENDIAN kernel config option which must be set to build such a kernel. If cross compiling, CROSS_COMPILE must point to a suitable toolchain (compiled for the powerpc64le-linux and powerpcle-linux targets). Signed-off-by:
Ian Munsie <imunsie@au1.ibm.com> Signed-off-by:
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Anton Blanchard authored
There are a number of KVM issues with little endian builds. We are working on fixing them, but in the meantime disable it. Signed-off-by:
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Anton Blanchard authored
pnv_pci_setup_bml_iommu was missing a byteswap of a device tree property. Signed-off-by:
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Anton Blanchard authored
Sparse caught an issue where opal_set_rtc_time was incorrectly byteswapping. Also fix a number of sparse warnings. Signed-off-by:
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Benjamin Herrenschmidt authored
The powernv exception handlers are not ready to take exceptions in little endian mode, so disable them. Signed-off-by: -
Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Alistair Popple authored
Signed-off-by:
Alistair Popple <alistair@popple.id.au> Signed-off-by:
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Alistair Popple authored
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Alistair Popple authored
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Alistair Popple authored
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Anton Blanchard authored
We need to distinguish between big endian and little endian environments, so fix uname to return the right thing. Signed-off-by:
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Anton Blanchard authored
We need to fix some endian issues in our memcpy code. For now just enable the generic memcpy routine for little endian builds. Signed-off-by:
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Anton Blanchard authored
We need to fix some endian issues in our checksum code. For now just enable the generic checksum routines for little endian builds. Signed-off-by:
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Anton Blanchard authored
Things are complicated by the fact that VSX elements are big endian ordered even in little endian mode. 8 byte loads and stores also write to the top 8 bytes of the register. Signed-off-by:
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Anton Blanchard authored
Handle most unaligned load and store faults in little endian mode. Strings, multiples and VSX are not supported. Signed-off-by:
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Anton Blanchard authored
The TS_FPR macro selects the FPR component of a VSX register (the high doubleword). emulate_vsx is using this macro to get the address of the associated VSX register. This happens to work on big endian, but fails on little endian. Replace it with an explicit array access. Signed-off-by:
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Anton Blanchard authored
The alignment handler assumes big endian ordering when selecting the low word of a 64bit floating point value. Use the existing union which works in both little and big endian. Signed-off-by:
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Anton Blanchard authored
Use swab64/32/16 instead of open coding it. Signed-off-by:
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Benjamin Herrenschmidt authored
Create a trampoline that works in either endian and flips to the expected endian. Use it for primary and secondary thread entry as well as RTAS and OF call return. Credit for finding the magic instruction goes to Paul Mackerras Signed-off-by:
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Ian Munsie authored
This patch will have powerpc include the appropriate generic endianness header depending on what the compiler reports. Signed-off-by:
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Anton Blanchard authored
We always take signals in big endian which is wrong. Signals should be taken in native endian. Signed-off-by:
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Anton Blanchard authored
We need to set MSR_LE in kernel and userspace for little endian builds Signed-off-by:
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Anton Blanchard authored
The powerpc word-at-a-time functions are big endian specific. Bring in the x86 version in order to support little endian builds. Signed-off-by:
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Ian Munsie authored
This patch maps the MMIO functions for 32bit PowerPC to their appropriate instructions depending on CPU endianness. The macros used to create the corresponding inline functions are also renamed by this patch. Previously they had BE or LE in their names which was misleading - they had nothing to do with endianness, but actually created different instruction forms so their new names reflect the instruction form they are creating (D-Form and X-Form). Little endian 64bit PowerPC is not supported, so the lack of mappings (and corresponding breakage) for that case is intentional to bring the attention of anyone doing a 64bit little endian port. 64bit big endian is unaffected. [ Added 64 bit versions - Anton ] Signed-off-by:
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Anton Blanchard authored
The elements within VSX loads and stores are big endian ordered regardless of endianness. Our VSX context save/restore code uses lxvd2x and stxvd2x which is a 2x doubleword operation. This means the two doublewords will be swapped and we have to perform another swap to undo it. We need to do this on save and restore. Signed-off-by:
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Anton Blanchard authored
FPRs overlap the high 64bits of the first 32 VSX registers. The ptrace FP read/write code assumes big endian ordering and grabs the lowest 64 bits. Fix this by using the TS_FPR macro which does the right thing. Signed-off-by:
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Anton Blanchard authored
The FPRs overlap the high doublewords of the first 32 VSX registers. Fix TS_FPROFFSET and TS_VSRLOWOFFSET so we access the correct fields in little endian mode. If VSX is disabled the FPRs are only one doubleword in length so TS_FPROFFSET needs adjusting in little endian. Signed-off-by:
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