- 22 Feb, 2023 6 commits
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Dmitry Baryshkov authored
A530 has highest bank bit equal to 15 (like A540). Fix values written to REG_A5XX_RB_MODE_CNTL and REG_A5XX_TPL1_MODE_CNTL registers. Fixes: 1d832ab3 ("drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522639/ Link: https://lore.kernel.org/r/20230214020956.164473-3-dmitry.baryshkov@linaro.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
Rather than writing CP_PREEMPT_ENABLE_GLOBAL twice, follow the vendor kernel and set CP_PREEMPT_ENABLE_LOCAL register instead. a5xx_submit() will override it during submission, but let's get the sequence correct. Fixes: b1fc2839 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by:
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Douglas Anderson authored
If, for whatever reason, we're trying process adreno_runtime_resume() at the same time that a6xx_destroy() is running then things can go boom. Specifically adreno_runtime_resume() will eventually call a6xx_pm_resume() and that may try to resume the gmu. Let's grab the GMU lock as we're destroying the GMU. That will solve the race because a6xx_pm_resume() grabs the same lock. That makes the access of `gmu->initialized` in a6xx_gmu_resume() safe. We'll also return an error code in a6xx_gmu_resume() if we see that `gmu->initialized` was false. If this happens we'll bail out of the rest of a6xx_pm_resume(), which is good because the rest of that function is also not good to do if we're racing with a6xx_destroy(). Signed-off-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/521232/ Link: https://lore.kernel.org/r/20230202104822.1.I0e49003bf4dd1dead9be4a29dbee41f3b1236e48@changeidSigned-off-by:
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Thomas Zimmermann authored
Do not run drm_fb_helper_unprepare() if fbdev allocation fails. Avoids access to an uninitialized pointer. Original bug report is at [1]. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Fixes: 3fb1f62f ("drm/fb-helper: Remove drm_fb_helper_unprepare() from drm_fb_helper_fini()") Link: https://lore.kernel.org/oe-kbuild-all/202302220810.9dymwCQ8-lkp@intel.com/ # 1 Reviewed-by:
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Rob Clark authored
The error path cleanup expects that chain and syncobj are either NULL or valid pointers. But post_deps was not allocated with __GFP_ZERO. Fixes: ab723b7a ("drm/msm: Add syncobj support.") Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Patchwork: https://patchwork.freedesktop.org/patch/523051/ Link: https://lore.kernel.org/r/20230215235048.1166484-1-robdclark@gmail.com
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Rob Clark authored
Back-merge of previous cycles msm-fixes for kexec fix (to avoid merge conflict) Signed-off-by:
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- 30 Jan, 2023 1 commit
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Rob Clark authored
The existing no-op shims for when PM_DEVFREQ (or an individual governor) only do half the job. The governor specific config/tuning structs need to be available to avoid compile errors in drivers using devfreq. Fixes: 6563f60f ("drm/msm/gpu: Add devfreq tuning debugfs") Signed-off-by:
MyungJoo Ham <myungjoo.ham@samsung.com> Acked-by:
Chanwoo Choi <cw00.choi@samsung.com> Patchwork: https://patchwork.freedesktop.org/patch/519801/ Link: https://lore.kernel.org/r/20230123153745.3185032-1-robdclark@gmail.com
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- 26 Jan, 2023 9 commits
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Dmitry Baryshkov authored
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe flag, but after the commit 854f6f1c ("drm/msm/dpu: update the qos remap only if the client type changes") it sets the flag late, after all the qos functions have updated QoS programming. Move the flag update back to the place where it happened before the mentioned commit to let the pipe be programmed according to its current RT/non-RT state. Fixes: 854f6f1c ("drm/msm/dpu: update the qos remap only if the client type changes") Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/516239/ Link: https://lore.kernel.org/r/20221229191856.3508092-2-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0. Change the catalog entry accordingly. Signed-off-by:
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Dmitry Baryshkov authored
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case. Signed-off-by:
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Dmitry Baryshkov authored
On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are preparing to convert the MSM8960 to use DT clocks properties (rather than global clock names), register the OF clock provider. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519211/ Link: https://lore.kernel.org/r/20230119132219.2479775-5-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Replace parent_names usage with parent_data. Note, that this makes the PLL default to board's `pxo_board' clock rather than just `pxo' clock, as we are on a way to deprecate the global cxo/pxo clocks. Signed-off-by:
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Dmitry Baryshkov authored
Eventually all HDMI PHYs are going to provide the HDMI PLL clock to the MMCC. Add #clock-cells property required to provide the HDMI PLL clock to other devices. Signed-off-by:
Rob Herring <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/519213/ Link: https://lore.kernel.org/r/20230119132219.2479775-3-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Add pxo clock to the 8960 bindings (used by the HDMI PLL) Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519206/ Link: https://lore.kernel.org/r/20230119132219.2479775-2-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
It was left unnoticed during the review that even if there is no OPP table in device tree, one will be created by a call to the function devm_pm_opp_set_clkname(). This leads to dsi_mgr_bridge_mode_valid() rejecting all modes if DT contains no OPP table for the DSI host. Rework dsi_mgr_bridge_mode_valid() to handle this case by actually checking that the table is populated with frequency entries before returning an error. Fixes: 8328041b ("drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()") Signed-off-by:
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Marijn Suijten authored
Add missing DSC hardware block register ranges to the snapshot utility to include them in dmesg (on MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) and the kms debugfs file. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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- 24 Jan, 2023 14 commits
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check the return value in order to avoid the NULL pointer dereference. Fixes: 1cff7440 ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by:
Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by:
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check pstates in order to avoid the NULL pointer dereference. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check cstate in order to avoid the NULL pointer dereference in __drm_atomic_helper_crtc_reset. Fixes: 1cff7440 ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by:
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Dmitry Baryshkov authored
Correct the CTL size on sm8450 platform. This fixes the incorrect merge of sm8350 support, which unfortunately also touched the SM8450 setup. Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by:
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Dmitry Baryshkov authored
Use the values from the vendor DTs to set ubwc_swizzle in the catalog. Signed-off-by:
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Dmitry Baryshkov authored
The field ubwc_static was removed from struct dpu_mdp_cfg some time ago. Drop the corresponding kerneldoc now. Fixes: 544d8b96 ("drm/msm/dpu: update UBWC config for sm8150 and sm8250") Signed-off-by:
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Dmitry Baryshkov authored
Using strncpy can result in non-NULL-terminated destination string. Use strscpy instead. This fixes following warning: drivers/gpu/drm/msm/msm_fence.c: In function ‘msm_fence_context_alloc’: drivers/gpu/drm/msm/msm_fence.c:25:9: warning: ‘strncpy’ specified bound 32 equals destination size [-Wstringop-truncation] 25 | strncpy(fctx->name, name, sizeof(fctx->name)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: f97decac ("drm/msm: Support multiple ringbuffers") Signed-off-by: -
Dmitry Baryshkov authored
Add missing DPU_CLK_CTRL_WB2 to sc7180_mdp clocks array. Fixes: 51e4d60e ("drm/msm/dpu: add writeback support for sc7180") Signed-off-by:
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Dmitry Baryshkov authored
Describe DSI supplies used on apq8064 (vdda-supply) and msm8994/96 (vcca-supply). Signed-off-by:
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Dmitry Baryshkov authored
Some platforms might use less than full 4 lanes DSI interface. Allow using any amount of lanes starting from 1 up to 4. Signed-off-by:
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Dmitry Baryshkov authored
APQ8064 requires listing four clocks in the assigned-clocks / assigned-clock-parents properties. Account for that. Signed-off-by:
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Dmitry Baryshkov authored
Stop mentioning #address-cells/#size-cells which are defined in display/dsi-controller.yaml. Use unevaluatedProperties instead of additionalProperties to allow skipping properties defined in other schema files. Signed-off-by:
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Bryan O'Donoghue authored
Each compatible has a different set of clocks which are associated with it. Add in the list of clocks for each compatible. Acked-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519080/ Link: https://lore.kernel.org/r/20230118171621.102694-3-bryan.odonoghue@linaro.orgSigned-off-by:
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Bryan O'Donoghue authored
Currently we do not differentiate between the various users of the qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one compatible string but, the hardware does have some significant differences in the number of clocks. To facilitate documenting the clocks add the following compatible strings - qcom,apq8064-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,qcm2290-dsi-ctrl Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format while we do so. Several MDSS yaml files exist which document the dsi sub-node. For each existing SoC MDSS yaml, provide the right dsi compat string. Acked-by:
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- 22 Jan, 2023 10 commits
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Dmitry Baryshkov authored
Merge display-related changes targeting Qualcomm DRM MSM driver. Notable changes: DPU, DSI, MDSS: - Support for SM8350, SM8450 SM8550 and SC8280XP platform Core: - Added bindings for SM8150 (driver support already present) DPU: - Partial support for DSC on SM8150 and SM8250 - Fixed color transformation matrix being lost on suspend/resume DP: - Support for DP on SDM845 and SC8280XP platforms - HPD fixes - Support for limiting DP link rate via DT property, this enables support for HBR3 rates. DSI: - Validate display modes according to the DSI OPP table - DSI PHY support for the SM6375 platform - Fixed byte intf clock selection for 14nm PHYs MDP5: - Schema conversion to YAML Misc fixes as usual Signed-off-by:
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Dmitry Baryshkov authored
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi', 'msm-next-lumag-mdp5' and 'msm-next-lumag-mdp4' into msm-next-lumag DPU, DSI, MDSS: - Support for SM8350, SM8450 SM8550 and SC8280XP platform Core: - Added bindings for SM8150 (driver support already present) DPU: - Partial support for DSC on SM8150 and SM8250 - Fixed color transformation matrix being lost on suspend/resume DP: - Support for DP on SDM845 and SC8280XP platforms - HPD fixes - Support for limiting DP link rate via DT property, this enables support for HBR3 rates. DSI: - Validate display modes according to the DSI OPP table - DSI PHY support for the SM6375 platform - Fixed byte intf clock selection for 14nm PHYs MDP5: - Schema conversion to YAML Misc fixes as usual Signed-off-by: -
Konrad Dybcio authored
v2.5.0 support was originally added for SC7280, but this hw is also present on SM8350, which has one more DSI host. Bump up the dsi count and fill in the register of the secondary host to allow it to probe. This should not have any adverse effects on SC7280, as the secondary CTRL will only be touched if it's defined, anyway. Fixes: 65c391b3 ("drm/msm/dsi: Add DSI support for SC7280") Signed-off-by:
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Dmitry Baryshkov authored
According to the vendor kernel, byte intf clock rate should be a half of the byte clock only when DSI PHY version is above 2.0 (in other words, 10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently MSM DSI code handles only the second part of the clause (C-PHY vs D-PHY), skipping DSI PHY version check, which causes issues on some of 14nm DSI PHY platforms (e.g. qcm2290). Move divisor selection to DSI PHY code, pass selected divisor through shared timings and set byte intf clock rate accordingly. Cc: Loic Poulain <loic.poulain@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
When converting from .txt to .yaml we didn't include descriptions for the existing regulator supplies. - vdd - vdda - vddio Add those descriptions into the yaml now as they were prior to the conversion. In the .txt description we marked these regulators as required, however, that requirement appears to have been in error. Taking the example of sc7180-trogdor-wormdingler.dtsi. The avdd and avee come from GPIO controlled external regulators, not the SoC and in this case there's no need for vddio to power an I/O bus. Similarly the regulators for the LCD are controlled by the panel driver not by the dsi-ctrl driver. It would be possible to connect a different type of panel to the DSI bus here in which case we may or may not want to make use of vdd, vdda or vddio. This is also the case for older chipsets like apq8064, msm8916 etc the vdd* regulators in the dsi-ctrl block are helpers not dependencies. Add the description of vdd, vdda and vddio back in for the existing upstream dts where vdd, vdda or vddio are already declared but, don't declare those regulators required - they are not SoC requirements. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Acked-by:
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Konrad Dybcio authored
On some SoCs (hello SM6375) vdds-supply is not wired to any smd-rpm or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line, which is voted for in the DSI ctrl node. Signed-off-by:
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Konrad Dybcio authored
SM6375 uses a boring standard 7nm PHY. Add a configuration entry for it. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
SM6375 has a single 7nm DSI PHY. Document it. Signed-off-by:
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Abhinav Kumar authored
Currently there is no protection against a user trying to set an unsupported mode on DSI. Implement a check based on the opp table whether the byte clock for the mode can be supported by validating whether an opp table entry exists. For devices which have not added opp table support yet, skip this check otherwise it will break bootup on those devices. changes in v3: - make the comment shorter - handle all errors except ENODEV Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/15Reported-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Abhinav Kumar authored
Re-arrange the dsi_calc_pclk method to two helpers, one to compute the DSI byte clk and the other to compute the pclk. This makes the separation of the two clean and also allows clients to compute and use the dsi byte clk separately. changes in v2: - move the assignments to definition lines Signed-off-by:
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