- 10 Apr, 2024 10 commits
-
-
Alex Deucher authored
Covers GPU page fault debugging and adds a reference to umr. v2: update client ids to include SQC/G v3: Remove duplicate text v4: add umr documentation link, fix typo Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
shaoyunl authored
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
-
Tim Huang authored
While doing multiple S4 stress tests, GC/RLC/PMFW get into an invalid state resulting into hard hangs. Adding a GFX reset as workaround just before sending the MP1_UNLOAD message avoids this failure. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
-
Yang Wang authored
refine function signature of amdgpu_aca_get_error_data(); Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
-
Li Ma authored
There is a new DCN veriosn 3.5.1 need to load Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
-
Lijo Lazar authored
For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got aborted. In such cases, reset the device during resume phase. This is a workaround till a proper solution is finalized. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Sunil Khatri authored
Add FW information of all the IP's in the devcoredump. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
-
Lang Yu authored
Otherwise the old one will be used during GPU reset. That's not expected. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
-
Lijo Lazar authored
Downgrade to debug information when IBs are skipped. Also, use dev_* to identify the device. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
-
Yang Wang authored
v1: add a new enumeration type to identify device attribute node, this method is relatively more efficient compared with 'strcmp' in update_attr() function. v2: rename device_attr_type to device_attr_id. Signed-off-by:
Ma Jun <majun@amd.com> Reviewed-by:
-
- 27 Mar, 2024 30 commits
-
-
Alex Deucher authored
There are cases where soft reset seems to succeed, but does not, so always use mode1/2 for now. Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
-
Harish Kasiviswanathan authored
Currently, with F32 HWS GPU reset is only when unmap queue fails. However, if compute queue doesn't repond to preemption request in time unmap will return without any error. In this case, only preemption error is logged and Reset is not triggered. Call GPU reset in this case also. Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
-
Johannes Weiner authored
An errant disk backup on my desktop got into debugfs and triggered the following deadlock scenario in the amdgpu debugfs files. The machine also hard-resets immediately after those lines are printed (although I wasn't able to reproduce that part when reading by hand): [ 1318.016074][ T1082] ====================================================== [ 1318.016607][ T1082] WARNING: possible circular locking dependency detected [ 1318.017107][ T1082] 6.8.0-rc7-00015-ge0c8221b72c0 #17 Not tainted [ 1318.017598][ T1082] ------------------------------------------------------ [ 1318.018096][ T1082] tar/1082 is trying to acquire lock: [ 1318.018585][ T1082] ffff98c44175d6a0 (&mm->mmap_lock){++++}-{3:3}, at: __might_fault+0x40/0x80 [ 1318.019084][ T1082] [ 1318.019084][ T1082] but task is already holding lock: [ 1318.020052][ T1082] ffff98c4c13f55f8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: amdgpu_debugfs_mqd_read+0x6a/0x250 [amdgpu] [ 1318.020607][ T1082] [ 1318.020607][ T1082] which lock already depends on the new lock. [ 1318.020607][ T1082] [ 1318.022081][ T1082] [ 1318.022081][ T1082] the existing dependency chain (in reverse order) is: [ 1318.023083][ T1082] [ 1318.023083][ T1082] -> #2 (reservation_ww_class_mutex){+.+.}-{3:3}: [ 1318.024114][ T1082] __ww_mutex_lock.constprop.0+0xe0/0x12f0 [ 1318.024639][ T1082] ww_mutex_lock+0x32/0x90 [ 1318.025161][ T1082] dma_resv_lockdep+0x18a/0x330 [ 1318.025683][ T1082] do_one_initcall+0x6a/0x350 [ 1318.026210][ T1082] kernel_init_freeable+0x1a3/0x310 [ 1318.026728][ T1082] kernel_init+0x15/0x1a0 [ 1318.027242][ T1082] ret_from_fork+0x2c/0x40 [ 1318.027759][ T1082] ret_from_fork_asm+0x11/0x20 [ 1318.028281][ T1082] [ 1318.028281][ T1082] -> #1 (reservation_ww_class_acquire){+.+.}-{0:0}: [ 1318.029297][ T1082] dma_resv_lockdep+0x16c/0x330 [ 1318.029790][ T1082] do_one_initcall+0x6a/0x350 [ 1318.030263][ T1082] kernel_init_freeable+0x1a3/0x310 [ 1318.030722][ T1082] kernel_init+0x15/0x1a0 [ 1318.031168][ T1082] ret_from_fork+0x2c/0x40 [ 1318.031598][ T1082] ret_from_fork_asm+0x11/0x20 [ 1318.032011][ T1082] [ 1318.032011][ T1082] -> #0 (&mm->mmap_lock){++++}-{3:3}: [ 1318.032778][ T1082] __lock_acquire+0x14bf/0x2680 [ 1318.033141][ T1082] lock_acquire+0xcd/0x2c0 [ 1318.033487][ T1082] __might_fault+0x58/0x80 [ 1318.033814][ T1082] amdgpu_debugfs_mqd_read+0x103/0x250 [amdgpu] [ 1318.034181][ T1082] full_proxy_read+0x55/0x80 [ 1318.034487][ T1082] vfs_read+0xa7/0x360 [ 1318.034788][ T1082] ksys_read+0x70/0xf0 [ 1318.035085][ T1082] do_syscall_64+0x94/0x180 [ 1318.035375][ T1082] entry_SYSCALL_64_after_hwframe+0x46/0x4e [ 1318.035664][ T1082] [ 1318.035664][ T1082] other info that might help us debug this: [ 1318.035664][ T1082] [ 1318.036487][ T1082] Chain exists of: [ 1318.036487][ T1082] &mm->mmap_lock --> reservation_ww_class_acquire --> reservation_ww_class_mutex [ 1318.036487][ T1082] [ 1318.037310][ T1082] Possible unsafe locking scenario: [ 1318.037310][ T1082] [ 1318.037838][ T1082] CPU0 CPU1 [ 1318.038101][ T1082] ---- ---- [ 1318.038350][ T1082] lock(reservation_ww_class_mutex); [ 1318.038590][ T1082] lock(reservation_ww_class_acquire); [ 1318.038839][ T1082] lock(reservation_ww_class_mutex); [ 1318.039083][ T1082] rlock(&mm->mmap_lock); [ 1318.039328][ T1082] [ 1318.039328][ T1082] *** DEADLOCK *** [ 1318.039328][ T1082] [ 1318.040029][ T1082] 1 lock held by tar/1082: [ 1318.040259][ T1082] #0: ffff98c4c13f55f8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: amdgpu_debugfs_mqd_read+0x6a/0x250 [amdgpu] [ 1318.040560][ T1082] [ 1318.040560][ T1082] stack backtrace: [ 1318.041053][ T1082] CPU: 22 PID: 1082 Comm: tar Not tainted 6.8.0-rc7-00015-ge0c8221b72c0 #17 3316c85d50e282c5643b075d1f01a4f6365e39c2 [ 1318.041329][ T1082] Hardware name: Gigabyte Technology Co., Ltd. B650 AORUS PRO AX/B650 AORUS PRO AX, BIOS F20 12/14/2023 [ 1318.041614][ T1082] Call Trace: [ 1318.041895][ T1082] <TASK> [ 1318.042175][ T1082] dump_stack_lvl+0x4a/0x80 [ 1318.042460][ T1082] check_noncircular+0x145/0x160 [ 1318.042743][ T1082] __lock_acquire+0x14bf/0x2680 [ 1318.043022][ T1082] lock_acquire+0xcd/0x2c0 [ 1318.043301][ T1082] ? __might_fault+0x40/0x80 [ 1318.043580][ T1082] ? __might_fault+0x40/0x80 [ 1318.043856][ T1082] __might_fault+0x58/0x80 [ 1318.044131][ T1082] ? __might_fault+0x40/0x80 [ 1318.044408][ T1082] amdgpu_debugfs_mqd_read+0x103/0x250 [amdgpu 8fe2afaa910cbd7654c8cab23563a94d6caebaab] [ 1318.044749][ T1082] full_proxy_read+0x55/0x80 [ 1318.045042][ T1082] vfs_read+0xa7/0x360 [ 1318.045333][ T1082] ksys_read+0x70/0xf0 [ 1318.045623][ T1082] do_syscall_64+0x94/0x180 [ 1318.045913][ T1082] ? do_syscall_64+0xa0/0x180 [ 1318.046201][ T1082] ? lockdep_hardirqs_on+0x7d/0x100 [ 1318.046487][ T1082] ? do_syscall_64+0xa0/0x180 [ 1318.046773][ T1082] ? do_syscall_64+0xa0/0x180 [ 1318.047057][ T1082] ? do_syscall_64+0xa0/0x180 [ 1318.047337][ T1082] ? do_syscall_64+0xa0/0x180 [ 1318.047611][ T1082] entry_SYSCALL_64_after_hwframe+0x46/0x4e [ 1318.047887][ T1082] RIP: 0033:0x7f480b70a39d [ 1318.048162][ T1082] Code: 91 ba 0d 00 f7 d8 64 89 02 b8 ff ff ff ff eb b2 e8 18 a3 01 00 0f 1f 84 00 00 00 00 00 80 3d a9 3c 0e 00 00 74 17 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 5b c3 66 2e 0f 1f 84 00 00 00 00 00 53 48 83 [ 1318.048769][ T1082] RSP: 002b:00007ffde77f5c68 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [ 1318.049083][ T1082] RAX: ffffffffffffffda RBX: 0000000000000800 RCX: 00007f480b70a39d [ 1318.049392][ T1082] RDX: 0000000000000800 RSI: 000055c9f2120c00 RDI: 0000000000000008 [ 1318.049703][ T1082] RBP: 0000000000000800 R08: 000055c9f2120a94 R09: 0000000000000007 [ 1318.050011][ T1082] R10: 0000000000000000 R11: 0000000000000246 R12: 000055c9f2120c00 [ 1318.050324][ T1082] R13: 0000000000000008 R14: 0000000000000008 R15: 0000000000000800 [ 1318.050638][ T1082] </TASK> amdgpu_debugfs_mqd_read() holds a reservation when it calls put_user(), which may fault and acquire the mmap_sem. This violates the established locking order. Bounce the mqd data through a kernel buffer to get put_user() out of the illegal section. Fixes: 445d85e3 ("drm/amdgpu: add debugfs interface for reading MQDs") Cc: stable@vger.kernel.org # v6.5+ Reviewed-by:Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Johannes Weiner <hannes@cmpxchg.org> Signed-off-by:
-
Lang Yu authored
Share same codes with 4.0.5 and enable collaborate mode for VPE. Signed-off-by:
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Acked-by:
-
Lang Yu authored
Align with FW changes. Signed-off-by:
-
Xi Liu authored
[WHY & HOW] DCN351 and DCN35 should use the same bounding box and IP settings. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Xi Liu <xi.liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
-
Aric Cyr authored
This version brings along following fixes: - Fix some bound and NULL check - Fix nonseamless transition from ODM + MPO to ODM + subvp - Allow Z8 when stutter threshold is not met - Remove plane and stream pointers from dc scratch - Remove read/write to external register - Increase number of hpo dp link encoders - Increase clock table size - Add new IPS config mode - Build scaling params when a new plane is appended - Refactor DML2 interfaces - Allow idle opts for no flip case on PSR panel Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
-
Muhammad Ahmed authored
[why] Driver crashes when pipe idx not set properly [how] Add code to skip the pipe that idx not set properly Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
-
Anthony Koo authored
- Add Display PHY FSM command interface for automated testing Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
-
Dillon Varone authored
[WHY&HOW] Converting the watermark set structure to a union and modifying some interfaces to accommodate future usage. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
-
Alvin Lee authored
[Why&How] Remove several plane and stream pointers from dc for code refactoring. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
-
Sridevi Arvindekar authored
[Why] Number of hpo dp2 link encoders is increased. Instances are changed. [How] Increased size in resource pool, init for each instance Reviewed-by:
Sridevi Arvindekar <sridevi.arvindekar@amd.com> Tested-by:
-
Sung Joon Kim authored
[why&how] To prevent out of bounds error, we need to increase the clock table size. Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
-
Bhawanpreet Lakha authored
[Why&How] Some panels don't meet the stutter threshold (4k etc), this leads to power regressions. Allow z8 for panels that don't meet the threshold but support PSR/replay Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Tested-by:
-
Bhawanpreet Lakha authored
[Why&How] Some panels don't meet the stutter threshold (4k etc), this leads to power regressions. Allow z8 for panels that don't meet the threshold but support PSR/replay Reviewed-by:
-
Nicholas Kazlauskas authored
[Why] We don't have a way to specify IPS2 for display off but RCG only for static screen and local video playback. [How] Add a new setting that allows RCG only when displays are active but IPS2 when all displays are off. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
-
Roman Li authored
[Why] NumFclkLevelsEnabled is used for DcfClocks bounds check instead of designated NumDcfClkLevelsEnabled. That can cause array index out-of-bounds access. [How] Use designated variable for dcn35 DcfClocks bounds check. Fixes: a8edc9cc ("drm/amd/display: Fix array-index-out-of-bounds in dcn35_clkmgr") Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
-
George Shen authored
[Why] MPC flow rate control is not needed for DCN30 and above. Current logic that uses it can result in underflow for certain edge cases (such as DSC N422 + ODM combine + 422 left edge pixel). [How] Remove MPC flow rate control logic and programming for DCN30 and above. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
-
Wenjing Liu authored
[why & how] We are boundling changes in plane state and build scaling params together. This is to simplify DML code so DML doesn't need to build scaling params. We are also avoiding rebuilding scaling params for planes without scaling changes. Reviewed-by:
-
Wenjing Liu authored
[why] when ODM + MPO is used for all 4 available pipes. Pipe transition will be nonseamless. Phantom OTG master pipe reuses the secondary OPP head pipe. There is no possible seamless path to transit to the new state. The correct logic would be to reuse a secondary DPP pipe as the phantom OTG master pipe. This way we are able to first transit the minimal transtion state of new and then transit to new state seamlessly. current New (nonseamless) ________________________ ________________________ | plane0 slice0 stream0| | plane0 slice0 stream0| |DPP0----OPP0----OTG0----| |DPP0----OPP0----OTG0----| | plane1 | | | | plane0 slice1 | | |DPP2----| | | |DPP2----OPP2----| | | plane0 slice1 | | | plane0 slice0 stream1| |DPP1----OPP1----| | |DPP1----OPP1----OTG1----| | plane1 | | | plane0 slice1 | | |DPP3----| | |DPP3----OPP3----| | |________________________| |________________________| New (seamless) New (minimal transition) ________________________ ________________________ | plane0 slice0 stream0| | plane0 slice0 stream0| |DPP0----OPP0----OTG0----| |DPP0----OPP0----OTG0----| | plane0 slice1 | | | plane0 slice1 | | |DPP1----OPP1----| | |DPP1----OPP1----| | | plane0 slice0 stream1| |________________________| |DPP2----OPP2----OTG2----| | plane0 slice1 | | |DPP3----OPP3----| | |________________________| [how] Try to acquire free pipes used as secondary DPP pipes from current state before try to acquire any free pipes for new OTG master pipe. Reviewed-by:
-
Wenjing Liu authored
[why&how] In some platform out_transfer_func may not be popualted. We need to check for null before dereferencing it. Fixes: d2dea1f1 ("drm/amd/display: Generalize new minimal transition path") Reviewed-by:
-
Sohaib Nadeem authored
[why&how] Add the missing null check before dereference for dc_stream_status* Fixes: 2d5bb791 ("drm/amd/display: Implement update_planes_and_stream_v3 sequence") Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
Sohaib Nadeem <sohaib.nadeem@amd.com> Tested-by:
-
Dillon Varone authored
[Why&How} Some interfaces needed changes to support future architectures. Reviewed-by:
-
Dillon Varone authored
[Why&How] These additional callbacks to DC will be required for the DML2 wrapper. Also consolidate common callbacks for projects to a single location for maintenance. Reviewed-by:
-
Sung Joon Kim authored
[why&how] We need to remove the reference to these registers to prevent any usage in the future. Reviewed-by:
-
Taimur Hassan authored
[Why] Previous patch to allow DTBCLK disable didn't address boot case. Driver thinks DTBCLK is disabled by default, so we don't send disable message to PMFW. DTBCLK is then enabled at idle desktop on boot, burning power. [How] Set dtbclk_en to true on boot so that disable message is sent during first commit. Fixes: 27750e17 ("drm/amd/display: Allow DTBCLK disable for DCN35") Reviewed-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
-
Natanel Roizenman authored
[WHY] Previously, we'd disabled HPO whenever an HPO display was disconnected. This caused other HPO displays to blank whenever one was unplugged. [HOW] This change restricts HPO enable/disable to dce110_apply_ctx_to_hw and adds a helper function (dce110_is_hpo_enabled) that returns true if any HPO displays are present in a context. We compare the current and previous dc ctx to check whether HPO is transitioning from on to off or vice versa, and adjust the HPO state accordingly. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Natanel Roizenman <natanel.roizenman@amd.com> Tested-by:
-
Sung Joon Kim authored
[why & how] There were some fixes in dcn35 that need to be ported over to dcn351 to prevent any regression. Signed-off-by:
Liu, Xi (Alex) <xiliu102@amd.com> Signed-off-by:
-
Hamza Mahfooz authored
We need to re-enable idle power optimizations after entering PSR. Since, we get kicked out of idle power optimizations before entering PSR (entering PSR requires us to write to DCN registers, which isn't allowed while we are in IPS). Fixes: a9b1a4f6 ("drm/amd/display: Add more checks for exiting idle in DC") Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
-
Alvin Lee authored
[Why & How] There is a corner case where a single PSR panel fails to enter idle optimizations if the panel is not flipping (no planes or DPMS_OFF == true). This is because the panel will not enter PSR if it's not flipping, but this will prevent the FW idle opt path from being executed. To handle this case we will allow entry to idle opt from driver side even when a PSR panel is connected under the following scenarios: 1. Only a single PSR panel is connected 2. PSR panel is not flipping Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
-
