1. 05 Nov, 2012 3 commits
    • Patil, Rachna's avatar
      input: TSC: ti_tscadc: set FIFO0 threshold Interrupt · 30af55f9
      Patil, Rachna authored
      Code currently uses FIFO1 threshold interrupt.
      since this is a MFD, Dedicating FIFO0 to touchscreen
      and making way for other devices to use FIFO1 as well.
      The FIFO can be shared between 2 devices but since the
      interrupt used is threshold interrupt on FIFO1, we would
      end up having wrong interrupts. Hence changing the same.
      Signed-off-by: default avatarPatil, Rachna <rachna@ti.com>
      Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
      30af55f9
    • Patil, Rachna's avatar
      input: TSC: ti_tscadc: Add Step configuration as platform data · d1fb5743
      Patil, Rachna authored
      There are 16 programmable Step Configuration
      registers which are used by the sequencer.
      Program the Steps in order to configure a channel
      input to be sampled. If the same step is applied
      several times, the coordinate values read are more
      accurate.
      Hence we provide the user an option of how many steps
      should be configured.
      
      For ex: If this value is assigned as 4, This means that
      4 steps are applied to read x co-ordinate and 4 steps to read
      y co-ordinate. Furtheron the interrupt handler already
      holds code to use delta filter and report the best value
      out of these values to the input sub-system.
      Signed-off-by: default avatarPatil, Rachna <rachna@ti.com>
      Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
      d1fb5743
    • Patil, Rachna's avatar
      input: TSC: ti_tscadc: Correct register usage · 33f5cc60
      Patil, Rachna authored
      This patch cleans up the wrong register definitions
      and usage for touchscreen controller.
      Bit masks were not defined earlier.
      
      For ex: consider a register define as:
      write(xyz, ABC)
      ABC is expected to be written to register bits 0-11.
      Here we see that value written is as expected, but this write
      is also affecting all the remaining bits of xyz.
      The remaining bits hold the default value as 0 and the write
      also sets it to zero. Hence wrong usage were not causing user
      visible bugs.
      Due to these reasons it was difficult to follow when
      compared with TRM.
      
      Unused definitions are also removed.
      Since there is change in some naming convention because of
      all the above mentioned reasons, the same has been
      updated throughout the code.
      Bit declarations are grouped to increase readability.
      Signed-off-by: default avatarPatil, Rachna <rachna@ti.com>
      Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
      33f5cc60
  2. 04 Nov, 2012 1 commit
  3. 03 Nov, 2012 15 commits
  4. 02 Nov, 2012 21 commits