- 27 Jan, 2017 40 commits
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Christian König authored
Give kernel allocations a higher priority cause it is often more work to swap them back in. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Roger.He <Hongbo.He@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Keeping groups of BOs on the LRU is to time consuming on command submission. Instead use the newly added BO priority to give a certain eviction order. v2: agd: trivial warning fix Signed-off-by:
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Christian König authored
This way the driver can specify a priority for a BO which has the effect that a BO is only evicted when all other BOs with a lower priority are evicted first. Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Signed-off-by:
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Christian König authored
Not allowing errors here is completely pointless and actually dangerous cause trying to continue on an error can cause an endless loop. Reviewed-by:
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Xiangliang Yu authored
For virt, freed mailbox irq should be handled in hw fini, not hw init. Correct it. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Xiangliang Yu authored
Reboot process will call HW fini functions of IP blocks. For virt, need to send event three before hw fini and send event four after hw fini. Signed-off-by:
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Tom St Denis authored
So we can determine which device the entry is before connecting a display. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Monk Liu authored
for non-VM submit which is from kernel side, no need to switch buffer at all. Signed-off-by:
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Monk Liu authored
SR-IOV requires the preamble. Signed-off-by:
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Monk Liu authored
no need to set it per ib_schedule(), hw won't override this polling address. Signed-off-by:
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Monk Liu authored
to support SRIOV preemption. v2: fix emit_frame_size Signed-off-by:
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Monk Liu authored
To determine whether the context uses GPUVM or not. Signed-off-by:
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Monk Liu authored
those package need to insert into ring buffer for SRIOV case. they are used to let CP do preemption. Signed-off-by:
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Monk Liu authored
Write multiple dwords to the ring. Signed-off-by:
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Monk Liu authored
META-DATA is used in GFX cmd submit, we have two format suit for META-DATA-init, one is legacy and another is for chained-ib preempt, which is used in vulkan UMD. v2: drop use CP version number to judge if chain-ib supports or not, we wait for it mature Signed-off-by:
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Rex Zhu authored
Fix up the powergating logic. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Ack-by:
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Nils Wallménius authored
The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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Andrey Grodzovsky authored
Make pflip atomic friendly. Split the fuinction into whatever can fail part and the actual flip submit part. Call the pre-submit function before atomic states are swapped so in case of error we can fail the IOCTL. v2: Update due to target_vblank code change. Fix identetation. Change return type for amdgpu_crtc_submit_flip to void v3: agd: fix formatting Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Switching to -ENOMEM resolves a hang in case the driver uses this function in atomic code path. v2: Update commit message. v3: Remove forcing -EINVAL in case of amdgpu_bo_pin fail since there is no apparent reason for not just passing through the the return value. Signed-off-by:
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Julia Lawall authored
Use BUG_ON instead of a if condition followed by BUG. Generated by: scripts/coccinelle/misc/bugon.cocci Reviewed-by:
Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Alex Deucher authored
Difference families may have different numbers of rings. Use the variable rather than a hardcoded number. Reviewed-by:
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Nicolai Hähnle authored
Unlock the resv lock only if we were the ones to lock it in the first place. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
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Nicolai Hähnle authored
ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of the newly allocated buffer is used and must explicitly be locked. Uninterruptible w/w locks without an acquire context are always successful. v2: use ww_mutex_lock Signed-off-by:
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Huang Rui authored
Fixes: 9e8590861e9 ('drm/amdgpu: add parse clock gating state') Reported-by:Huang Rui <ray.huang@amd.com> Reviewed-by:
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Xiangliang Yu authored
Current amdgpu reset process only works on bare-metal and for SRIOV many inside it need re-work to adapt to vf device. This is a temporary workaround to skip gpu reset. Signed-off-by:
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Xiangliang Yu authored
Virtual display is default setting for virtualization, enable it. Signed-off-by:
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Xiangliang Yu authored
Call VI virtualization functions if device is Vf. Signed-off-by:
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Xiangliang Yu authored
For gpu vf device, first need to request full gpu access before accessing gpu registers, and release full gpu access after the access is done. Signed-off-by:
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Xiangliang Yu authored
VI has asic specific virt support, which including mailbox and golden registers init. Signed-off-by:
shaoyunl <Shaoyun.Liu@amd.com> Reviewed-by:
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Xiangliang Yu authored
Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by:
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Xiangliang Yu authored
For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. v2: agd: rebase Signed-off-by:
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Xiangliang Yu authored
Add new flag to define gpu runtime that is out of full gpu access. Signed-off-by:
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Xiangliang Yu authored
Implement emit_rreg/wreg function for kiq ring. Signed-off-by:
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Xiangliang Yu authored
During virtual runtime, need to send command to kiq ring to read/write GPU registers. Add two interface to support the two actions. Signed-off-by:
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Monk Liu authored
Make sure the CSA is mapped. v2: agd: rebase. Signed-off-by:
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Monk Liu authored
for SRIOV usage, CSA is only used per device and each VM will map on it. Signed-off-by:
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Monk Liu authored
and implement CSA functions in this file Signed-off-by:
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Nicolai Hähnle authored
Skip amdgpu_gem_va_update_vm otherwise. Also clean up the check for the non-shadow page tables using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc v2: actually check bo->shadow instead of just checking bo twice Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Nicolai Hähnle authored
Skip amdgpu_gem_va_update_vm when shadow the page directory is swapped out. Clean up the check for non-shadow BOs as well using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc Signed-off-by:
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Nicolai Hähnle authored
Signed-off-by:
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