- 06 Aug, 2024 16 commits
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Aric Cyr authored
This version brings along the following: - SPL improvements. - Address coverity issues. - DML2 fixes. - Code cleanup. - DIO and DCCG refactor. - Improve the PSR state. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
Remove function pointers that were never used. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Rodrigo Siqueira authored
Add missing debug registers for DCN32. Reviewed-by:
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Rodrigo Siqueira authored
Initialize the field dcc_meta_propagation_delay_us with 10 ms. Reviewed-by:
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Rodrigo Siqueira authored
Add missing register programming for mcache in DCN401. Reviewed-by:
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Rodrigo Siqueira authored
DCN_MINIMUM_DISPCLK_Khz and DCN_MINIMUM_DPPCLK_Khz is declared twice. This commit removes that duplication. Reviewed-by:
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Rodrigo Siqueira authored
The commit 5034b935 ("drm/amd/display: Modify DHCUB waterwark structures and functions") introduced a code refactor for DCHUB, but during the merge process into amd-staging-drm-next, the program det segments were removed. This commit adds the DET segment programming for DCN35. Fixes: 5034b935 ("drm/amd/display: Modify DHCUB waterwark structures and functions") Reviewed-by:
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Alvin Lee authored
P-State force programming is handled entirely by FW in FAMS2. Remove any programming from driver side to prevent incorrect programming from driver side (which may override FW programming) Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by:
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Sung Lee authored
[WHY] Cursor position code had improper offsets in scaled modes. [HOW] Adjust cursor scaling to account for cursor offsets properly. Reviewed-by:
Sung Lee <sunglee@amd.com> Tested-by:
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Rodrigo Siqueira authored
In the commit c2cec7a872b6 ("drm/amd/display: Wake DMCUB before sending a command for replay feature"), replaced dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd in multiple areas, but due to merge issues the replacement of this function in the dmub_replay_copy_settings was missed. This commit replaces the old dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd. Fixes: 3601a35a ("drm/amd/display: Wake DMCUB before sending a command for replay feature") Reviewed-by: -
Rodrigo Siqueira authored
SPL has a control field for controlling the two pixels per container that is not in use yet. This commit adds a proper initialization for this feature. Reviewed-by:
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Rodrigo Siqueira authored
Move the lb_memory_config close to the pixel format enums to improve the code readability. Reviewed-by:
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Cruise authored
The link index wasn't updated for the AUX reply notification. Get link index based on DPIA instance for AUX reply notification. Signed-off-by:
Cruise <Cruise.Hung@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Alex Hung authored
CalculateSwathAndDETConfiguration_params_st's UnboundedRequestEnabled is a pointer (i.e. dml_bool_t *UnboundedRequestEnabled), and thus p->UnboundedRequestEnabled checks its address, not bool value. To check value, *p->UnboundedRequestEnabled is used instead. This fixes 1 REVERSE_INULL issue reported by Coverity. Signed-off-by:
Alex Hung <alex.hung@amd.com> Reviewed-by:
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Daniel Sa authored
[WHY] In dcn401 we read clock values before FW is loaded. These incorrect values cause the driver to believe that we are running higher clocks than what we actually have. This then causes corruption/underflow for the eGPU. [HOW] When new values are read from HW, update internal structures to propagate the new/correct value. Fixes issue Signed-off-by:
Daniel Sa <Daniel.Sa@amd.com> Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Aux transfer retries path does not support dp tunneling. [How] Based on ddc pin check, aux will be issued in legacy path or DMUB. Signed-off-by:
Eric Yang <eric.yang@amd.com> Tested-by:
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- 27 Jul, 2024 24 commits
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Hansen Dsouza authored
Add new enable and disable functions based on DCCG spec. Signed-off-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] It's currently hard coded to 256 when it should be using the SOC provided values. This can result in corruption with linear surfaces where we prefetch more PTE than the buffer can hold. [How] Update the min page size correctly for the plane. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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Alex Hung authored
Variables, used as denominators and maybe not assigned to other values, should not be 0. bytes_per_element_y & bytes_per_element_c are initialized by get_bytes_per_element() which should never return 0. This fixes 10 DIVIDE_BY_ZERO issues reported by Coverity. Signed-off-by:
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Alex Hung authored
Functions get_per_method_common_meta and get_expanded_strategy_list can return null and thus it is necessary to check their returned values before dereferencing. This fixes 3 NULL_RETURNS issues reported by Coverity. Signed-off-by:
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Cruise authored
The DP tunnel AUX reply is received through Outbox1. Print the Outbox1 status if an issue occurs. Signed-off-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Hansen Dsouza authored
Add new enable and disable functions based on DCCG spec. Signed-off-by:
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Thomas Weißschuh authored
Instead of manually passing around 'struct edid *' and its size, use 'struct drm_edid', which encapsulates a validated combination of both. As the drm_edid_ can handle NULL gracefully, the explicit checks can be dropped. Also save a few characters by transforming '&array[0]' to the equivalent 'array' and using 'max_t(int, ...)' instead of manual casts. Signed-off-by:
Thomas Weißschuh <linux@weissschuh.net> Signed-off-by:
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Thomas Weißschuh authored
Instead of manually passing around 'struct edid *' and its size, use 'struct drm_edid', which encapsulates a validated combination of both. As the drm_edid_ can handle NULL gracefully, the explicit checks can be dropped. Also save a few characters by transforming '&array[0]' to the equivalent 'array' and using 'max_t(int, ...)' instead of manual casts. Signed-off-by:
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Alex Deucher authored
We only need to skip this on modern APUs. It's required on older APUs as it's where start_smu gets called from. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3502 Fixes: 064d9243 ("drm/amd/pm: avoid to load smu firmware for APUs") Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
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Sunil Khatri authored
Problem: IP dump right now is done post suspend of all IP's which for some IP's could change power state and software state too which we do not want to reflect in the dump as it might not be same at the time of hang. Solution: IP should be dumped as close to the HW state when the GPU was in hung state without trying to reinitialize any resource. Acked-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Alex Hung authored
sampling_rate is an uint8_t but is assigned an unsigned int, and thus it can overflow. As a result, sampling_rate is changed to uint32_t. Similarly, LINK_QUAL_PATTERN_SET has a size of 2 bits, and it should only be assigned to a value less or equal than 4. This fixes 2 INTEGER_OVERFLOW issues reported by Coverity. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Ilya Bakoulin authored
Need to use cm3_helper function with DCN401 to avoid cases where high RGB component values can get set to zero if using the TF curve generated by cm_helper. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] When pre-OS firmware enables display support for displays that operate the DIG in 2 pixels per cycle processing modes the inferred pixel rate from get_pixel_clk_frequency_100hz does not account for the true pixel rate since we're outputting 2 per cycle past the stream encoder. This causes seamless boot validation to abort early. [How] Add a new stream encoder function for getting pixels per cycle from the stream encoder. If the pixels per cycle is greater than 1 and the driver policy is to enable 2 pixels per cycle for post-OS then allow seamless boot to continue. Signed-off-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Tom Chung authored
[Why] After resume the system, the new_crtc_state->vrr_infopacket does not synchronize with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. The previous patch causes a PSR SU regression that cannot let panel go into self-refresh mode. [How] Reset the VRR config during resume to force update the VRR config later. Fixes: eb6dfbb7 ("drm/amd/display: Reset freesync config before update new state") Signed-off-by:
Tom Chung <chiahsuan.chung@amd.com> Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Tested-by:
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Tom Chung authored
[Why & How] Add a missing PSR state to make the dmub_psr_get_state() return a correct PSR state. Signed-off-by:
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Charlene Liu authored
[why] dmubfw added a new event type, update amdgpu to avoid "notify type 6 invalid" Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Charlene Liu authored
[why] immediate_disable_crtc does not reset ODM. if switching to disable_crtc which will disable ODM as well. i.e. need to restore ODM mem cfg at reenable it at end of w/a. Signed-off-by:
Xi (Alex) Liu <xi.liu@amd.com> Tested-by:
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Michael Chen authored
MES firmware requires larger log buffer for gfx12. Allocate proper buffer respectively for gfx11 and gfx12. Signed-off-by:
Michael Chen <michael.chen@amd.com> Acked-by:
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Alex Hung authored
[WHAT & HOW] dc_state_get_stream_status can return null, and therefore null must be checked before stream_status is used. This fixes 1 NULL_RETURNS issue reported by Coverity. Signed-off-by:
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Alex Hung authored
[WHAT & HOW] dc_link is null checked previously in the same function, indicating it might be null as reported by Coverity. This fixes 1 FORWARD_NULL issue reported by Coverity. Signed-off-by:
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Alex Hung authored
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned long long (64 bits). This can be fixed by casting integer to unsigned long long to force 64 bits results. This fixes 2 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Signed-off-by:
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Alvin Lee authored
Use debug option for disabling unbounded req in DML21 Signed-off-by:
Austin Zheng <Austin.Zheng@amd.com> Tested-by:
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Bhuvanachandra Pinninti authored
Moved files to respective folders to improve DIO code. Signed-off-by:
Bhuvanachandra Pinninti <bpinnint@amd.com> Reviewed-by:
Martin Leung <martin.leung@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] If we aren't entering RCG/IPS2 or CLKSTOP is not supported by PMFW then we should be requesting a dispclk value of 0MHz to PMFW. Currenly we run at max clock since there's an assumption in APU clock table formulation where we can run at any DISPCLK at any state so the real clock value ends up as 1200Mhz - the maximum. [How] Set to 0 instead of the minimum value in the state array. Signed-off-by:
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