- 19 May, 2009 30 commits
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Kumar Gala authored
In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Its feasible based on how the PCI address map is setup that the region of PCI address space used for MSIs differs for each PHB on the same SoC. Instead of assuming that the address mappes to CCSRBAR 1:1 we read PEXCSRBAR (BAR0) for the PHB that the given pci_dev is on. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The MPC8568/9 chips support MSIs on PCIe so no reason not to enable them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
We we build with dma_addr_t as a 64-bit quantity we get: drivers/dma/fsldma.c: In function 'fsl_chan_xfer_ld_queue': drivers/dma/fsldma.c:625: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'fsl_dma_chan_do_interrupt': drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'of_fsl_dma_probe': drivers/dma/fsldma.c:927: warning: cast to pointer from integer of different Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Dan Williams <dan.j.williams@intel.com>
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Anton Vorontsov authored
For serial flash support we need to: - Add QE Par IO Bank E device tree node, a GPIO from this bank is used for SPI chip-select line; - Add serial-flash node; - Add proper module alias into of/base.c. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
Select HAS_RAPIDIO symbol and add rio nodes for MPC8568E-MDS and MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
Note that eSDHC and DUART0 are mutually exclusive on MPC8569E-MDS boards. Default option is DUART0, so eSDHC is disabled by default. U-Boot will fixup device tree if eSDHC should be used instead of DUART0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
This patch fixes bogus reg = <> property in the localbus node, and fixes interrupt property (should be "interrupts"). Also add node for NAND support. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
fsl,exec-units-mask should be 0xbfe to include SNOW unit in MPC8569E's security engine. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
This patch adds PCI IDs for MPC8569 and MPC8569E processors, plus adds appropriate quirks for these IDs, and thus makes PCI-E actually work on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Between the addition of the ecm/mcm law nodes and the fact that the get_immrbase() has been using the range property of the SoC to determine the base address of CCSR space we no longer need the reg property at the soc node level. It has been ill specified and varied between device trees to cover either the {e,m}cm-law node, some odd subset of CCSR space or all of CCSR space. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe node. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
The MPC8569 is similiar to the MPC8568. It doubles the number of QUICC Engine RISC cores from 2 to 4. Removes eTSECs, TLU and adds the eSDHC controller. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
In the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at 1000Base-T simultaneously. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
Keep an unique machine def for the MPC8568 MDS board to handle some subtle differences between the future MDS board. Also set the bcsrs in setup_arch() only for mpc8568_mds because other mds has different bcsr settings. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Removed the need for asm/mpc86xx.h as it was only used in mpc86xx_smp.c and just moved the defines it cared about into there. Also fixed up the ioremap to only map the one 4k page we need access to and to iounmap when we are done. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Kill of some old defines and macros that we no longer use like CPM_MAP_ADDR and CPM_IRQ_OFFSET. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Becky Bruce authored
Also, convert them to resource_size_t (which is unsigned long on 64-bit, so it's not a change there). We will be using these on fsl 32b to indicate the start and size address of memory that the pci controller can actually reach - this is needed to determine if an address requires bounce buffering. For now, initialize them to a standard value; in the near future, the value will be calculated based on how the inbound windows are programmed. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the MPX coherency module. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the ECM coherency module. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The rstcr register mapping code was written sometime ago before of_iomap() existed. We can use it and clean up the code a bit and get rid of one user of get_immrbase() in the process. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Becky Bruce authored
The new dts places most of the devices in physical address space above 32-bits, which allows us to have more than 4GB of RAM present. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Refactor the check to determine if the quirk is applicable to the boards into one inline function so we only have to change one place to add more boards that the quirks might be applicable to. Also removed a warning related to unused temp variable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The cell-index property isn't used on PCI nodes and is ill defined. Remove it for now and if someone comes up with a good reason and consistent definition for it we can add it back Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Michael Ellerman authored
It's still in the git history if anyone wants it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- 17 May, 2009 5 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6Linus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6: PM: check sysdev_suspend(PMSG_FREEZE) return value
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Jeff Mahoney authored
This adds CONFIG_REISERFS_FS_XATTR protection from reiserfs_permission. This is needed to avoid warnings during file deletions and chowns with xattrs disabled. Signed-off-by: Jeff Mahoney <jeffm@suse.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Jeff Mahoney authored
This avoids an Oops in open_xa_root that can occur when deleting a file with xattrs disabled. It assumes that the xattr root will be there, and that is not guaranteed. Signed-off-by: Jeff Mahoney <jeffm@suse.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Jeff Mahoney authored
With xattr cleanup even with xattrs disabled, much of the initial setup is still performed. Some #ifdefs are just not needed since the options they protect wouldn't be available anyway. This cleans those up. Signed-off-by: Jeff Mahoney <jeffm@suse.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/penberg/slab-2.6Linus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/slab-2.6: mm: SLOB fix reclaim_state mm: SLUB fix reclaim_state slub: add Documentation/ABI/testing/sysfs-kernel-slab slub: enforce MAX_ORDER
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- 16 May, 2009 5 commits
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Linus Torvalds authored
Ian Campbell noticed that since "Eliminate thousands of warnings with gcc 3.2 build" (commit 57adc4d2) all WARN_ON()'s currently appear to come from warn_slowpath_null(), eg: WARNING: at kernel/softirq.c:143 warn_slowpath_null+0x1c/0x20() because now that warn_slowpath_null() is in the call path, the __builtin_return_address(0) returns that, rather than the place that caused the warning. Fix this by splitting up the warn_slowpath_null/fmt cases differently, using a common helper function, and getting the return address in the right place. This also happens to avoid the unnecessary stack usage for the non-stdargs case, and just generally cleans things up. Make the function name printout use %pS while at it. Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Johannes Weiner <hannes@cmpxchg.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Hugh Dickins <hugh@veritas.com> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6Linus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6: piix: The Sony TZ90 needs the cable type hardcoding icside: register second channel of version 6 PCB ide-tape: remove back-to-back REQUEST_SENSE detection
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git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6Linus Torvalds authored
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: ACPI: Idle C-states disabled by max_cstate should not disable the TSC ACPI: idle: fix init-time TSC check regression ACPI processor: reset the throttling state once it's invalid ACPI processor: introduce module parameter processor.ignore_tpc ACPI, i915: build fix ACPI: suspend: restore BM_RLD on resume ACPI: resume: re-enable SCI-enable workaround thermal: fix off-by-1 error in trip point trigger condition eeepc-laptop: unregister_rfkill_notifier on failure asus-laptop: fix input keycode eeepc-laptop: support for super hybrid engine (SHE) eeepc-laptop: Work around rfkill firmware bug eeepc-laptop: report brightness control events via the input layer eeepc-laptop: fix wlan rfkill state change during init ACPI: suspend: don't let device _PS3 failure prevent suspend ACPI: power: update error message ACPI: video: DMI workaround another broken Acer BIOS enabling display brightness ACPICA: use acpi.* modparam namespace ACPI video: dmi check for broken _BQC on Acer Aspire 5720
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Alan Cox authored
The Sony TZ90 needs the cable type hardcoding. See bug #12734 Signed-off-by: Alan Cox <alan@linux.intel.com> Reported-by: Jonathan E. Snow <jesnow@uh.edu> [bart: port it from ata_piix to piix and give reporter the proper credit] Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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Sergei Shtylyov authored
The second IDE channel of version 6 PCB is not being registered anymore since the commit 48c3c107 (ide: add struct ide_host (take 3)). Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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