- 30 Sep, 2015 40 commits
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Matt Roper authored
Just pull the info out of the CRTC state structure rather than staging it in an additional structure. Note that we use cstate->active rather than intel_crtc->active which may appear to be a change in behavior. However since we're no longer trying to recalculate watermarks during the "pipe off" stage of a modeset, intel_crtc->active and cstate->active should always be identical when watermarks are calculated (at least for ILK-style platforms). v2: Clarify reasoning for cstate->active and add a WARN_ON to the code to assert that it really is always identical to intel_crtc->active as expected. Signed-off-by:Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Matt Roper authored
Just pull the info out of the plane state structure rather than staging it in an additional structure. v2: Add 'visible' condition to sprites_scaled so that we don't limit the WM level when the sprite isn't enabled. (Ville) Signed-off-by: -
Matt Roper authored
In commit commit e4ca0612 Author: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Date: Wed Jul 8 15:31:52 2015 +0200 drm/i915: Don't forget to mark crtc as inactive after disable we added extra watermark updates to all of the .crtc_disable() entrypoints to avoid problems problems with system resume on SKL. Those disable entrypoints are currently called in just two places in the driver: intel_atomic_commit (i.e., during a modeset) and intel_crtc_disable_noatomic (which is called during hardware readout). It seems that this extra watermark recalculation should only be important in the latter case (which happens during a resume operation); the former case should always have appropriate watermark programming happening at other points in the modeset sequence. Let's move the watermark update out of the .crtc_disable() entrypoints and place it directly in intel_crtc_disable_noatomic() so that it only happens on S3 resume and not during a regular modeset (since the existing watermark handling should properly update watermarks during normal atomic commits). Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: -
Imre Deak authored
The RC6 residency time unit is 833.33ns on BXT according to the specification, so update the calculation accordingly. Use the same way as CHV/VLV to divide by the corresponding frequency, as I think this is the more natural unit for what the HW does internally. v2: - add missing IS_BROXTON check (Ville) Testcase: igt/pm_rc6_residency Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Alex Dai authored
GuC expects two bits for Render and Media domain separately when driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for Render and bit 1 is for Media domain. v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating v1: Add parameters definition to avoid magic value Signed-off-by:
Alex Dai <yu.dai@intel.com> Reviewed-by:
Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by:
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Ville Syrjälä authored
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Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Ville Syrjälä authored
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Łukasz Daniluk authored
Added checks for available slices, subslices and EUs for Broadwell. This information is filled in intel_device_info and is available to user with GET_PARAM. Added checks for enabled slices, subslices and EU for Broadwell. This information is based on available counts but takes power gated slices into account. It can be read in debugfs. Introduce new register defines that contain information on slices on Broadwell. v2: - Introduce GT_SLICE_INFO register - Change Broadwell sseu_device_status function to use GT_SLICE_INFO register instead of RPCS register - Undo removal of dev_priv variables in Cherryview and Gen9 sseu_device_satus functions v3: - Fix style issues v4: - Corrected comment - Reverted reordering of defines Cc: Jeff Mcgee <jeff.mcgee@intel.com> Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by:
Łukasz Daniluk <lukasz.daniluk@intel.com> Reviewed-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
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Julia Lawall authored
Remove unneeded NULL test. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x; @@ -if (x != NULL) \(kmem_cache_destroy\|mempool_destroy\|dma_pool_destroy\)(x); // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Jani Nikula authored
Previously we've relied on having basically one backlight and one backlight type per platform. This is already a bit quirky with PMIC PWM support on VLV/CHV platforms with MIPI DSI. In the foreseeable future we'll have at least DPCD based backlight control on eDP and DCS command based backlight control on MIPI DSI. Backlight is becoming more and more connector specific, so reflect this fact by making the backlight control hooks connector specific. This enables further work to reuse generic backlight code in intel_panel.c while adding more specific backlight code accessed via the hooks. Cc: Deepak M <m.deepak@intel.com> Cc: Yetunde Adebisi <yetundex.adebisi@intel.com> Signed-off-by:
Deepak M <m.deepak@intel.com> Reviewed-by:
Yetunde Adebisi <yetundex.adebisi@intel.com> Signed-off-by:
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Jani Nikula authored
Make the alternatives stand out better. Signed-off-by:
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Jani Nikula authored
It's more useful to limp on than bring the kernel down. Hitting this is a more likely event with BXT DSI, although care should be taken not to call the function for DSI. Signed-off-by:
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Ville Syrjälä authored
Replace the use of mem_freq/4 with czclk_freq in the vlv c0 residency calculations. Also deal with VLV_COUNT_RANGE_HIGH which affects all RCx residency counters. We have just enough bits to do this without intermediate divisions. Signed-off-by:
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Ville Syrjälä authored
We have the czclk frequency in dev_priv now, so let's just use it when converting the rc6 counters to milliseconds. This eliminates a bunch of hairy code that essentially tries to extract the czclk frequency using yet another method. v2: Fix typos in commit message (Imre) Reviewed-by:
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Ville Syrjälä authored
As with the cdclk, read out czclk from CCK as well. This gives us the real current value and avoids having to decode fuses and whatnot. Also store it in kHz under dev_priv like we do for cdlck since it's not just an rps related clock, and having it in kHz is more standard/convenient for some things. Imre also pointed out that we currently fail to read czclk on VLV, which means the PFI credit programming isn't working as expected. Signed-off-by:
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Vandana Kannan authored
Rename the DISPLAY_TRUNK_* and DISPLAY_FREQUENCY_* bits to CCK_... instead of DISPLAY_... to make it clear they apply to all CCK clock control registers. Suggested by Ville. Signed-off-by:
Vandana Kannan <vandana.kannan@intel.com> Reviewed-by:
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Rasmus Villemoes authored
->stolen->start has type u64 aka unsigned long long; relying on the difference (effectively cast to int) for sorting is wrong. It wouldn't be a problem in practice if the values compared are always within INT_MAX of each other (so that the difference is actually representable in an int), but 440fd528 ("drm/mm: Support 4 GiB and larger ranges") strongly suggests that's not the case. Note: atm we don't support more than about 1G of stolen, so this is impossible currenlty. Signed-off-by:
Rasmus Villemoes <linux@rasmusvillemoes.dk> [danvet: Add note that this is impossible currently.] Signed-off-by:
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Arun Siluvery authored
Signed-off-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by:
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
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Arun Siluvery authored
WA in this function should be ordered based on register address. The following order is suggested (Ville), instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg.h as it is not used anywhere else. Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg as it is not used anywhere else. Signed-off-by:
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Arun Siluvery authored
Dropping it because it is for pre-production stepping. Signed-off-by:
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Arun Siluvery authored
Updated WA with the name. Signed-off-by:
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Arun Siluvery authored
Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save an entry in WA array. Signed-off-by:
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Arun Siluvery authored
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Mika Kahola authored
This patch adds information of current and maximum CD clock frequency and pixel clock frequency information on 'i915_debugfs.c'. v2: - combined seperate patches for current CD clock, maximum CD clock and maximum pixel clock - space added between the frequency value and the unit Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
v2: Deal with _CURABASE too Signed-off-by:
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
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Ville Syrjälä authored
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