- 05 Mar, 2021 8 commits
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Wayne Lin authored
[Why] To support feature that calculates CRTC CRC value on specific region (crc window). [How] 1. Use debugfs to specify crtc crc window 2. Use vline0 IRQ to write crtc crc window Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wayne Lin authored
[Why & How] Find out that referring to crtc_state->crc_src is not thread safe. Move crc_src from dm_crtc_state to dm_irq_params to fix this. Signed-off-by:
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Tom St Denis authored
The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why & How] We use DMCUB outbox0 interrupt to log DMCUB trace buffer events as Linux kernel traces, so need to add some irq source related defination in the header files; Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Arunpravin authored
Remove unnecessary comments, enable restore mode using '|=' operator, fixes the alignment to improve the code readability. v2: Move all restoration flag check to bitwise '&' operator Signed-off-by:
Arunpravin <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Horace Chen authored
sienna cichlid needs one vf mode which allows vf to set and get clock status from guest vm. So now expose the required interface and allow some smu request on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send SMU request under sriov vf. OD use same command as getting pp table which is not allowed for sienna cichlid, so remove OD feature under sriov vf. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by:
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Evan Quan authored
Update the gpu_metrics interface implementations to use the latest upgraded data structures. V2: fit the data type change of energy_accumulator Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Evan Quan authored
To make sure they are naturally aligned. Also updating the data type for link_speed/width for future PCIE5 support. V2: define new structures with minor version bumped V3: update data type of energy_accumulator as 64bit and drop unnecessary padding members Signed-off-by:
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- 03 Mar, 2021 11 commits
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:59: drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in expansion of macro ‘AUX_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58: note: (near initialization for ‘aux_shift.AUX_SW_AUTOINCREMENT_DISABLE’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in expansion of macro ‘AUX_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in expansion of macro ‘AUX_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:181:2: note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56: note: (near initialization for ‘aux_mask.AUX_SW_AUTOINCREMENT_DISABLE’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in expansion of macro ‘AUX_SF’ Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
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Dan Carpenter authored
The hdcp_i2c_offsets[] array did not have an entry for HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE so it led to an off by one read overflow. I added an entry and copied the 0x0 value for the offset from similar code in drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c. I also declared several of these arrays as having HDCP_MESSAGE_ID_MAX entries. This doesn't change the code, but it's just a belt and suspenders approach to try future proof the code. Fixes: 4c283fda ("drm/amd/display: Add HDCP module") Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Colin Ian King authored
Currently the ioctl command RADEON_INFO_SI_BACKEND_ENABLED_MASK can copy back uninitialised data in value_tmp that pointer *value points to. This can occur when rdev->family is less than CHIP_BONAIRE and less than CHIP_TAHITI. Fix this by adding in a missing -EINVAL so that no invalid value is copied back to userspace. Addresses-Coverity: ("Uninitialized scalar variable) Cc: stable@vger.kernel.org # 3.13+ Fixes: 439a1cff ("drm/radeon: expose render backend mask to the userspace") Reviewed-by:Christian König <christian.koenig@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Chen Li authored
This may avoid debug confusion. Reviewed-by:
Chen Li <chenli@uniontech.com> Signed-off-by:
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Chen Li authored
The number of chunks/chunks_array may be passed in by userspace and can be large. Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Kevin Wang authored
the register offset isn't needed division by 4 to pass RREG32_PCIE() Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Kevin Wang authored
add SECUREDISPLAY TA firmware info in amdgpu_fimrware_info() Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Kevin Wang authored
refine PSP TA firmware info print in amdgpu_firmware_info(). Signed-off-by:
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Xiaojian Du authored
This patch is to correct the name of one function for vangogh. This function is used to print the clock levels of all kinds of IP components. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:298:33-38: WARNING: conversion to bool not needed here. Reported-by:
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- 02 Mar, 2021 21 commits
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Chen Li authored
The number of chunks/chunks_array may be passed in by userspace and can be large. It has been observed to cause kcalloc failures from trinity fuzzy test: WARNING: CPU: 0 PID: 5487 at mm/page_alloc.c:4385 __alloc_pages_nodemask+0x2d8/0x14d0 Obviously, the required order in this case is larger than MAX_ORDER. So, just use kvmalloc instead. Reviewed-by:
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Arnd Bergmann authored
clang points out that the new logic uses an always-uninitialized array index: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9810:38: warning: variable 'i' is uninitialized when used here [-Wuninitialized] timing = &edid->detailed_timings[i]; ^ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9720:7: note: initialize the variable 'i' to silence this warning My best guess is that the index should have been returned by the parse_hdmi_amd_vsdb() function that walks an array here, so do that. Fixes: f9b4f20c ("drm/amd/display: Add Freesync HDMI support to DM") Reviewed-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Colin Ian King authored
Currently if stream->signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and this is checked for > 0 at the end of the function. Ret should be initialized, I believe setting it to zero is a correct default. Addresses-Coverity: ("Uninitialized scalar variable") Fixes: bd0c064c ("drm/amd/display: Add return code instead of boolean for future use") Reviewed-by: -
Alex Deucher authored
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Alex Deucher authored
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Xiaogang Chen authored
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT interrupt(hpd, hpd_rx) by using work queue and uses single work_struct. If new interrupt is recevied before the previous handler finished, new interrupts(same type) will be discarded and driver just sends "amdgpu_dm_irq_schedule_work FAILED" message out. If some important hpd, hpd_rx related interrupts are missed by driver the hot (un)plug devices may cause system hang or instability, such as issues with system resume from S3 sleep with mst device connected. This patch dynamically allocates new amdgpu_dm_irq_handler_data for new interrupts if previous INTERRUPT_LOW_IRQ_CONTEXT interrupt work has not been handled. So the new interrupt works can be queued to the same workqueue_struct, instead of discard the new interrupts. All allocated amdgpu_dm_irq_handler_data are put into a single linked list and will be reused after. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses reminder of 64 bit division (modulus operator) , which is not supported by 32 bit platforms [how] Use div64 API for 64 bit modulus Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Bindu Ramamurthy<bindu.r@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses division operator for 64 bit division, which is not supported by 32 bit platforms [how] Use div64 API for 64 bit division Signed-off-by:
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Jonathan Kim authored
Request to stop DF performance counters is missing the actual write to the controller register. Reported-by:
Chris Freehill <chris.freehill@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Acked-by:
Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by:
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Dillon Varone authored
[Why?] HSplit should not affect DSC slice count. Can cause improper timings to be applied for certain modes. [How?] No longer change DSC Slice count based on HSplit. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Hugo Hu authored
[Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Tested-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Aric Cyr authored
DC version 3.2.125 brings improvements in multiple areas. In summary, we highlight: - DSC fixes - Enable ASSR - Firmware relase 0.0.54 - eDP interface refactor for multiple eDP Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] DMUB FW send trace event via outbox0 interrupt. Driver will handle it. Tested-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] GPINT timeout is causing PSR_STATE_0 to be returned when it shouldn't. We must guarantee that PSR is fully disabled before doing hw programming on driver-side. [How] Return invalid state if GPINT command times out. Let existing retry logic send the GPINT until successful. Tested-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Jake Wang authored
[Why & How] Some existing DC interfaces are optimized to return a single eDP link/stream. Refactored those DC interfaces to support multiple eDP. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Eryk Brol authored
[Why] Useful for testing when setting a max bpc value higher than the default is required [How] Allow for reading/writing of the max_requested_bpc property of the connector Tested-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Max.Tseng authored
[why] Add flag to build infopacket in SDP v1.3 format Tested-by:
Max.Tseng <Max.Tseng@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why] Currently the creation of link encoder objects is tightly coupled to the creation of link objects. Decoupling link encoder object creation is a preliminary step in the process of allowing link encoders to be dynamically assigned to links. [How] Add "minimal" link encoder objects which are not associated with any link until required. Tested-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
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Evan Quan authored
By using the information provided by PMFW when available. V2: put those structures shared around SMU V11 ASICs in smu_v11_0.h Signed-off-by:
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