- 06 Mar, 2024 3 commits
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Pierre-Eric Pelloux-Prayer authored
Using the ring_muxer without preemption adds overhead for no reason since mcbp cannot be triggered. Moving back to a single queue in this case also helps when high priority app are used: in this case the gpu_scheduler priority handling will work as expected - much better than ring_muxer with its 2 independant schedulers competing for the same hardware queue. This change requires moving amdgpu_device_set_mcbp above amdgpu_device_ip_early_init because we use adev->gfx.mcbp. Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
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Yang Wang authored
the dce dpm is not available on gfx 11.0.3 sriov device. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jesse Zhang authored
Remove the unused function - amdgpu_vm_pt_is_root_clean and remove the impossible condition v1: entries == 0 is not possible any more, so this condition could probably be removed (Felix) Signed-off-by:Jesse Zhang <jesse.zhang@amd.com> Suggested-by：Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
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- 04 Mar, 2024 13 commits
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Christian König authored
It turned out that executing the SET_Q_MODE packet on every submission creates to much overhead. Implement a workaround which allows skipping the SET_Q_MODE packet if subsequent submissions all use the same parameters. v2: add a NULL check for ring_obj Signed-off-by:
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Christian König authored
First of all calculating the number of dw to patch into a conditional execution is not something HW generation specific. This is just standard ring buffer calculations. While at it also reduce the BUG_ON() into WARN_ON(). Then instead of a random bit pattern use 0 as default value for the number of dw skipped, this way it's not mandatory any more to patch the conditional execution. And last make the address to check a parameter of the conditional execution instead of getting this from the ring. Signed-off-by:
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Ma Jun authored
Because the rpm_mode flag is already set when the driver is initialized, we use it directly for runtime suspend/resume instead of checking it again Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Ma Jun authored
Fix the pwm_mode value error which used for pwm1_enable setting Signed-off-by:
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Shashank Sharma authored
This patch changes the handling and lifecycle of vm->task_info object. The major changes are: - vm->task_info is a dynamically allocated ptr now, and its uasge is reference counted. - introducing two new helper funcs for task_info lifecycle management - amdgpu_vm_get_task_info: reference counts up task_info before returning this info - amdgpu_vm_put_task_info: reference counts down task_info - last put to task_info() frees task_info from the vm. This patch also does logistical changes required for existing usage of vm->task_info. V2: Do not block all the prints when task_info not found (Felix) V3: Fixed review comments from Felix - Fix wrong indentation - No debug message for -ENOMEM - Add NULL check for task_info - Do not duplicate the debug messages (ti vs no ti) - Get first reference of task_info in vm_init(), put last in vm_fini() V4: Fixed review comments from Felix - fix double reference increment in create_task_info - change amdgpu_vm_get_task_info_pasid - additional changes in amdgpu_gem.c while porting Cc: Christian Koenig <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Alex Deucher authored
Need to check the offset bits for values greater than 255. v2: also update amdgpu_dm_connector values. Suggested-by:
Mano Ségransan <mano.segransan@protonmail.com> Tested-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Add Display Manager specific changes for DCN3.5.1. Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Add DC support for DCN 3.5.1. Signed-off-by:
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Hamza Mahfooz authored
Add DCN3.5.1 interrupt support. Signed-off-by:
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Hamza Mahfooz authored
DMUB support is required to light-up displays. Signed-off-by:
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Hamza Mahfooz authored
Add register headers for DCN 3.5.1. Signed-off-by:
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Hamza Mahfooz authored
Add DCN3.5.1 ASIC identifiers. Signed-off-by:
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Jesse Zhang authored
fix the issue: "amdgpu: Failed to create process VM object". [Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm page table. But when clifo run. It also initializes a vm for a process device through the function kfd_process_device_init_vm and ensure the root PD is clean through the function amdgpu_vm_pt_is_root_clean. So they have a conflict, and clinfo always failed. v1: - remove all the pte_supports_ats stuff from the amdgpu_vm code (Felix) Signed-off-by:
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- 01 Mar, 2024 6 commits
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Bjorn Helgaas authored
After 4020c228 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)"), "ret" is unconditionally set later before being used, so there's point in initializing it and the associated comment is no longer meaningful. Remove the comment and the unnecessary initialization. Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 11b92df8. This conflicts with how compositors want to handle VRR. Now that compositors actually handle VRR, we probably don't need freesync video. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2985Acked-by:
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Alex Deucher authored
This reverts commit e94e787e. This conflicts with how compositors want to handle VRR. Now that compositors actually handle VRR, we probably don't need freesync video. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2985Acked-by:
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Melissa Wen authored
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6683 amdgpu_dm_connector_funcs_force() warn: variable dereferenced before check 'dc_link' (see line 6663) Fixes: 96717617 ("drm/amd/display: fix null-pointer dereference on edid reading") Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Tao Zhou authored
Both RAS UE and deferred errors need page retirement. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Li Ma authored
Add an if condition for gfx activity because the scaling has been changed after smu fw version 5d4600. And remove a warning log. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
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- 28 Feb, 2024 4 commits
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Eric Huang authored
The adev can be found from bo by amdgpu_ttm_adev(bo->tbo.bdev), and adev is also not used in the function amdgpu_amdkfd_map_gtt_bo_to_gart(). Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Asad Kamal authored
Fix mask used for esm ctrl register to get pcie link speed on smu_v11_0_3, smu_v13_0_2 & smu_v13_0_6 Fixes: 511a9555 ("drm/amd/pm: Add SMU 13.0.6 support") Fixes: c05d1c40 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)") Fixes: f1c37859 ("drm/amd/powerplay: add Arcturus support for gpu metrics export") Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Asad Kamal authored
Skip reporting pcie link width/speed on vfs for smu_v13_0_6 & smu_v13_0_2 Signed-off-by:
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Yang Wang authored
v1: enabel pp_od_clk_voltage node for gfx 9.4.3 SRIOV and BM. v2: add onevf check for gfx 9.4.3 v3: refine code check order to make function clearly. Signed-off-by:
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- 27 Feb, 2024 5 commits
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Alex Deucher authored
This reverts commit e490d60a. This causes hangs on SI when DC is enabled and errors on driver reboot and power off cycles. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3216 Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2755Reviewed-by:
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Srinivasan Shanmugam authored
This ensures that the memory mapped by ioremap for adev->rmmio, is properly handled in amdgpu_device_init(). If the function exits early due to an error, the memory is unmapped. If the function completes successfully, the memory remains mapped. Reported by smatch: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4337 amdgpu_device_init() warn: 'adev->rmmio' from ioremap() not released on lines: 4035,4045,4051,4058,4068,4337 Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Missing break statement in the ATOM_ARG_IMM case of a switch statement, adds the missing break statement, ensuring that the program's control flow is as intended. Fixes the below: drivers/gpu/drm/amd/amdgpu/atom.c:323 atom_get_src_int() warn: ignoring unreachable code. Fixes: d38ceaf9 ("drm/amdgpu: add core driver (v4)") Cc: Jammy Zhou <Jammy.Zhou@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Lijo Lazar authored
On SOCs with SMUv13.0.6, mode-2 reset takes a bit longer. Wait for 200ms before trying to restore config space after mode-2 reset. Signed-off-by:
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Mario Limonciello authored
This vendor specific property has never been used by userspace software and conflicts with the panel_power_savings sysfs file. That is a compositor and user could fight over the same data. Fixes: 63d0b872 ("drm/amd/display: add panel_power_savings sysfs entry to eDP connectors") Suggested-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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- 26 Feb, 2024 9 commits
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Lijo Lazar authored
On devices which have multi-partition nodes, keep partition id in location_id[31:28]. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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Tim Huang authored
This patch fixes a MES firmware boot failure issue when backdoor loading the MES firmware. MES firmware runtime DRAM size is changed to 512k, the driver needs to reserve this amount of memory in FB, otherwise adjacent memory will be overwritten by the MES firmware startup code. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
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Prike Liang authored
Currently, GPU resets can now be performed successfully on the Raven series. While GPU reset is required for the S3 suspend abort case. So now can enable gpu reset for S3 abort cases on the Raven series. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
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Ma Jun authored
It's unreasonable to use 0 as the power1_min_cap when OD is disabled. So, use the same lower limit as the value used when OD is enabled. Fixes: 19589468 ("drm/amd/pm: Support for getting power1_cap_min value") Signed-off-by:
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Victor Lu authored
VF should not program this register. Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
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Stanley.Yang authored
Check amdgpu_ras_mask to fix ineffective ras_mask setting due to special asic without sram ecc enable but with poison supported. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Lijo Lazar authored
If fatal error is detected, packet submission won't go through. Return error in such cases. Also, avoid waiting for fence when fatal error is detected. Signed-off-by:
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Lijo Lazar authored
For a RAS error that needs a full reset to recover, set the fatal error status. Clear the status once the device is reset. Signed-off-by:
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Srinivasan Shanmugam authored
Adds a check in the map_hw_resources function to prevent a potential buffer overflow. The function was accessing arrays using an index that could potentially be greater than the size of the arrays, leading to a buffer overflow. Adds a check to ensure that the index is within the bounds of the arrays. If the index is out of bounds, an error message is printed and break it will continue execution with just ignoring extra data early to prevent the buffer overflow. Reported by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_wrapper.c:79 map_hw_resources() error: buffer overflow 'dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id' 6 <= 7 drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_wrapper.c:81 map_hw_resources() error: buffer overflow 'dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id' 6 <= 7 Fixes: 7966f319 ("drm/amd/display: Introduce DML2") Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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