- 30 Aug, 2023 40 commits
-
-
Aric Cyr authored
This version brings along following fixes: - Ensure FS is enabled before sending request to DMUB for FS changes - Add check for PMFW hard min request complete - Save addr update in scratch before flip - Fix static screen detection setting - Write flip addr to scratch reg for subvp - set minimum of VBlank_nom - Correct unit conversion for vstartup - Roll back unit correction - Enable runtime register offset init for DCN32 DMUB - Refactor edp power control - PQ regamma end point - PQ tail accuracy - Expose mall capability Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Anthony Koo authored
- Remove unused flag otg_powered_down Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
-
Samson Tam authored
[Why] ignore_msa_timing_param indicates FS is capable but not necessarily enabled [How] add check for either allow_freesync or vrr_active_variable to confirm FS is enabled Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
-
Samson Tam authored
[Why] When we issue hard min request to PMFW, the ack back does not guarantee the request has been fulfilled. [How] Add new PMFW message to check if the hard min request has been completed. Returned bit mask indicates which clock requests are completed. Check PMFW version before using message Reviewed-by:
-
Alvin Lee authored
[Why & How] Fix a minor sequencing issue where the address update for a subvp flip should be saved in scratch registers before the actual flip Reviewed-by:
Austin Zheng <austin.zheng@amd.com> Acked-by:
-
SungHuai Wang authored
[WHY] OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3, but we still follow DCN2 to apply setting for OTG_STATIC_SCREEN_EVENT_MASK. [How] Add new function to apply correct settings for DCN3 series. Reviewed-by:
SungHuai Wang <danny.wang@amd.com> Tested-by:
-
benl authored
Add initial gfxhub 11.5 support. Signed-off-by:
benl <ben.li@amd.com> Signed-off-by:
-
Prike Liang authored
Add to IP discovery table. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
-
Lang Yu authored
Add initial implementation for mmhub 3.3.0. v2: squash in client id fix (Alex) Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Signed-off-by:
-
Lang Yu authored
Add new headers. v2: updates (Alex) Signed-off-by:
-
Prike Liang authored
Add to IP discovery table. Signed-off-by:
-
Lang Yu authored
Add to IP discovery table. Signed-off-by:
-
Aaron Liu authored
Add scheduler and kiq firmware support for gc_11_5_0. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
-
Aaron Liu authored
Add imu firmware support for gc_11_5_0. Signed-off-by:
-
Lang Yu authored
Enable KFD for GC 11.5.0. Signed-off-by:
-
Aaron Liu authored
Initialize golden setting for gc_11_5_0. v2: squash in latest golden updates (Alex) v3: squash in checkpatch fix (Alex) Signed-off-by:
-
Prike Liang authored
Initalize gfx 11.5.0 and set gfx hw configuration. Signed-off-by:
-
Prike Liang authored
Initialize vram attribute and VMHUB for GC 11.5.0. Signed-off-by:
-
Lang Yu authored
Add gc_11_5_0 headers. v2: updates (Alex) Signed-off-by:
-
Prike Liang authored
Add to IP discovery table. Signed-off-by:
-
benl authored
Add initial nbio 7.11 implementation. Signed-off-by:
-
benl authored
Add register headers. v2: Updates (Alex) v3: Updates (Alex) v4: Updates (Alex) Signed-off-by:
-
Prike Liang authored
Add 11.5.0 to IP discovery table. Signed-off-by:
-
Prike Liang authored
Disable clock gating and power gating on the early bring up phase. Signed-off-by:
-
Prike Liang authored
add GC 11.5.0 family Signed-off-by:
-
Lang Yu authored
Use 6.1.0 register offset and remove unused variable. v2: clean up logic (Alex) Signed-off-by:
-
Konstantin Meskhidze authored
Buffer 'afmt_status' of size 6 could overflow, since index 'afmt_idx' is checked after access. Fixes: 5cc4e5fc ("drm/radeon: Cleanup HDMI audio interrupt handling for evergreen") Co-developed-by:
Ivanov Mikhail <ivanov.mikhail1@huawei-partners.com> Signed-off-by:
Konstantin Meskhidze <konstantin.meskhidze@huawei.com> Signed-off-by:
-
Hamza Mahfooz authored
As made mention of in commit 4a2df0d1 ("drm/amd/display: Fixed non-native modes not lighting up"), we shouldn't call drm_mode_set_crtcinfo() once the crtc timings have been decided. Since, it can cause settings to be unintentionally overwritten. So, since dm_state is never NULL now, we can use old_stream to determine if we should call drm_mode_set_crtcinfo() because we only need to set the crtc timing parameters for entirely new streams. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Fixes: bd49f190 ("drm/amd/display: Always set crtcinfo from create_stream_for_sink") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
-
Asad Kamal authored
Critical Temperature needs to be reported in millidegree Celsius. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
-
Mangesh Gadre authored
rlc firmware does required setting, driver need not do it. Signed-off-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Lijo Lazar authored
Add a function to wait till bootloader has reached steady state. Signed-off-by:
-
Horace Chen authored
[What] Current SRIOV still using adev->clock.default_XX which gets from atomfirmware. But these fields are abandoned in atomfirmware long ago. Which may cause function to return a 0 value. [How] We don't need to check whether SR-IOV. For SR-IOV one-vf-mode, pm is enabled and VF is able to read dpm clock from pmfw, so we can use dpm clock interface directly. For multi-VF mode, VF pm is disabled, so driver can just react as pm disabled. One-vf-mode is introduced from GFX9 so it shall not have any backward compatibility issue. Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Lijo Lazar authored
BACO dummy mode could be set under reset conditions and that affects framebuffer access. Check If baco dummy mode is set, unset it if so. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
-
Alvin Lee authored
[Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
-
ChunTao Tso authored
[Why] If VBlank_nom is too small, it will cause VStartUP_Start smaller than VBackPorch + VSync width which is an invalid case for VStartUP_Start and where to send AS-SDP. [How] Setup a minimum value to VBlank_nom Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
-
Reza Amini authored
[why] vstartup is calculated to be a large number. it works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [how] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by:
Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by:
-
Ovidiu Bunea authored
[why] This Unit correction exposes a Replay corruption. [how] This reverts commit: commit dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Roll back unit conversion until Replay can fix their corruption. Fixes: dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
-
Aurabindo Pillai authored
[Why&How] DMUB subsystem was continuing to use compile time offset calculation for register access. Switch this to runtime calculation to stay consistent with rest of DC code. To enable this, an additional interface init_reg_offsets() are added to DMUB's hw_funcs struct. Asics with runtime register offset calculation enabled shall populate this hook with a fn pointer that will invoke the necessary macros to calculate the offset. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
-
Ian Chen authored
[Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by:
Ian Chen <ian.chen@amd.com> Tested-by:
-
Krunoslav Kovac authored
[WHY & HOW] PQ has a fixed range of 0-10,000 nits. Using 1=80 nits normalization, PQ should map to 1.0 for X=125.0 HW LUT used for interpolation does not have X=125 so it's interpolated. However, we cap Y to 1 for all X>=125. The closest larger HW point is 128. What we want is Y(128) such that interpolation through 125 gives 1.0. Such value is ~1.00256. Another change is to hardcode PQ table, we pretty much always have 1=80 normalization so the table can be static. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by:
-
