- 20 Mar, 2024 40 commits
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Tao Zhou authored
Support the query for both gfxhub and mmhub, also replace xcc_id with hub_inst. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tao Zhou authored
Add it for mmhub v1.8. Signed-off-by:
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Xiaojian Du authored
This will drm/amdgpu: add VCN sensor value for Vangogh. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Samson Tam authored
[Why] During init_pipes, otg master is not initialized. So mpc tree is still configured even if mpc bottom is not active [How] For pipes that have tg enabled, check their mpc tree and clear opp_list if mpc bottom is not active Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Samson Tam <samson.tam@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Yang Wang authored
refine aca error cache for mmhub v1.8 Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Pixel clock programming should be built per dcn revision, not hardcoded to use dcn20. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Stream clock source is a required parameter for DP DTO programming. Reviewed-by:
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Christian Koenig authored
The problem is that when (for example) 4k pages are replaced with a single 2M page we need to wait for change to be flushed out by invalidating the TLB before the PT can be freed. Solve this by moving the TLB flush into a DMA-fence object which can be used to delay the freeing of the PT BOs until it is signaled. V2: (Shashank) - rebase - set dma_fence_error only in case of error - add tlb_flush fence only when PT/PD BO is locked (Felix) - use vm->pasid when f is NULL (Mukul) V4: - add a wait for (f->dependency) in tlb_fence_work (Christian) - move the misplaced fence_create call to the end (Philip) V5: - free the f->dependency properly V6: (Shashank) - light code movement, moved all the clean-up in previous patch - introduce params.needs_flush and its usage in this patch - rebase without TLB HW sequence patch V7: - Keep the vm->last_update_fence and tlb_cb code until we can fix the HW sequencing (Christian) - Move all the tlb_fence related code in a separate function so that its easier to read and review V9: Addressed review comments from Christian - start PT update only when we have callback memory allocated V10: - handle device unlock in OOM case (Christian, Mukul) - added Christian's R-B Cc: Christian Koenig <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Acked-by:Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Tested-by:
Shashank Sharma <shashank.sharma@amd.com> Reviewed-by:
Christian Koenig <christian.koenig@amd.com> Signed-off-by:
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Yang Wang authored
refine aca error cache for gfx 9.4.3 Signed-off-by:
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Yang Wang authored
add new api to save error count into aca cache. Signed-off-by:
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Yang Wang authored
Add new types to distinguish between ACA error type and smu mca type. e.g.: the ACA_ERROR_TYPE_DEFERRED is not matched any smu mca valid bank channel, so add new type 'aca_smu_type' to distinguish aca error type and smu mca type. Signed-off-by:
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Srinivasan Shanmugam authored
pipe_ctx->plane_res.mpcc_inst is of a type that can only hold values between 0 and 255, so it's always greater than or equal to 0. Thus the condition 'pipe_ctx->plane_res.mpcc_inst >= 0' was always true and has been removed. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn35/dcn35_hwseq.c:1023 dcn35_calc_blocks_to_gate() warn: always true condition '(pipe_ctx->plane_res.mpcc_inst >= 0) => (0-255 >= 0)' Fixes: 6f8b7565 ("drm/amd/display: Add DCN35 HWSEQ") Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Adds descriptions for 'new_context', 'srf_updates', and 'surface_count', and removes the excess description for 'context'. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Function parameter or member 'new_context' not described in 'commit_minimal_transition_state_in_dc_update' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Function parameter or member 'srf_updates' not described in 'commit_minimal_transition_state_in_dc_update' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Function parameter or member 'surface_count' not described in 'commit_minimal_transition_state_in_dc_update' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Excess function parameter 'context' description in 'commit_minimal_transition_state_in_dc_update' Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c: In function ‘smu_v13_0_init_microcode’: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:108:52: warning: ‘%s’ directive output may be truncated writing up to 29 bytes into a region of size 23 [-Wformat-truncation=] 108 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); | ^~ ~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:108:9: note: ‘snprintf’ output between 12 and 41 bytes into a destination of size 30 108 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by:Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Sunil Khatri authored
adev is a global data structure and isn't expected to be NULL and hence removing the redundant adev check from the devcoredump code. Cc: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Suggested-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
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Nicholas Susanto authored
[Why] Underflow occurs when running netflix in a 4k144 eDP + 4k60 setup. Increasing DCFCLK or urgent latency watermark fixes the issue. Implementing this workaround for now while we figure out why this is happenning in DCN. [How] Enable urgent latency adjustment and match the reference to existing ASIC that also see increased latency at low FCLK. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Likun Gao authored
Support for atom_firmware_info_v3_5. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Hawking Zhang authored
To ensure GPU driver touch the local framebuffer until it is initialized by integrated firmware. Signed-off-by:
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Yang Wang authored
add amdgpu ras event id support to better distinguish different error information sources in dmesg logs. the following log will be identify by event id: {event_id} interrupt to inform RAS event {event_id} ACA logs {event_id} errors statistic since from current injection/error query {event_id} errors statistic since from gpu load Signed-off-by: -
Nicholas Kazlauskas authored
[Why] Leave disabled by default due to sequencing issues around power states where these flags aren't properly reset. [How] Allow re-enabling from DC debug option. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Acked-by:
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Zhigang Luo authored
if reading pf2vf data failed 30 times continuously, it means something is wrong. Need to trigger flr_work to recover the issue. also use dev_err to print the error message to get which device has issue and add warning message if waiting IDH_FLR_NOTIFICATION_CMPL timeout. Signed-off-by:
Zhigang Luo <Zhigang.Luo@amd.com> Acked-by:
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Xiaojian Du authored
This will add vclk and dclk sysfs node for some ASICs. Signed-off-by:
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Xiaojian Du authored
This will add VCN sensor value for SMU 13.0.4. Signed-off-by:
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Wenjing Liu authored
[why] In minial transitions state, ODM combine shouldn't be forced as it will make transition non seamless. The force ODM debug option is to control the end result not the intermediate transition. So we can temporarily disable ODM forcing when committing minimal transition state. [how] Backup stream ODM forcing option and clear it in minimal transition state. Once minimal transition state is released, we will restore the original debug option back. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Rodrigo Siqueira authored
[Why & How] Registers and offset are missing. Add it back Acked-by:
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Rodrigo Siqueira authored
[Why & How] This commit just drop some old comments and update a typo in another one. Acked-by:
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Sherry Wang authored
[Why] Hostvm should be enabled/disabled accordding to the status of riommu_active, but hostvm always be disabled on DCN31 which causes underflow [How] Set correct hostvm flag on DCN31 Acked-by:
Sherry Wang <Yao.Wang1@amd.com> Tested-by:
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Rodrigo Siqueira authored
[Why & How] Remove legacy code which is unnecessary. Acked-by:
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Rodrigo Siqueira authored
[Why & How] Enable legacy fast update for DCN314 Acked-by:
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Rodrigo Siqueira authored
[Why & How] DCN3_16_MIN_COMPBUF_SIZE_KB is defined in the dcn316_resource.c file. This header fit better in the dcn31_fpu.h together with similar defines. Acked-by:
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Mukul Joshi authored
This patch adds the following functionality: - Check the queue preemption status on all XCDs in a partition for GFX 9.4.3. - Update the queue preemption debug message to print the queue doorbell id for which preemption failed. - Change the signature of check preemption failed function to return a bool instead of uint32_t and pass the MQD manager as an argument. Suggested-by:
Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Mukul Joshi authored
Rename read_doorbell_id function to a more meaningful name, implying what it is used for. No functional change. Suggested-by:
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Asad Kamal authored
Report pcie link speed/width using metric table in case of one vf & if pmfw support is available, else report directly from registers in case of pf. Skip reporting it for other cases. v2: Skip multi-vf check(Lijo) Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Asad Kamal authored
Update PMFW interface headers for updated metrics table with pcie link speed and pcie link width Signed-off-by:
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Rodrigo Siqueira authored
[Why & How] If the driver has issues retrieving the MALL size for the specific hardware, it might fail since the current value is set to zero. This commit addresses this issue by adding a simple constant value to give the drive a chance to start. Acked-by:
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Alex Hung authored
[Why & How] This fixes indentations and adjust spaces for better readability and code styles. Acked-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Alex Hung authored
[Why & How] dcn32_smu_transfer_wm_table_dram_2_smu is defined twice so one is removed. Also adjust prototype orders. Acked-by:
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Rodrigo Siqueira authored
[Why & How] Enable 2to1 ODM policy for DCN35 Acked-by:
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Rodrigo Siqueira authored
In some of the merge conflict fixes, one '+' was accidentally left at the beginning of the line. Fortunately, this did not cause any major issues since it acted as a number signal. This commit addresses this issue by removing the extra '+'. Acked-by:
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Rodrigo Siqueira authored
[Why & How] Remove redundant code Acked-by:
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