- 18 Apr, 2023 18 commits
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Rodrigo Siqueira authored
When the commit fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") was merged, we missed some parts associated with the MCLK switch. This commit adds all the missing parts. Fixes: fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wesley Chalmers authored
[WHY] It is possible to commit state multiple times in rapid succession with FAMS enabled; if each of these commits were to set optimized_required, then the user may see latency. [HOW] fw_based_mclk_switching is currently not used in dc->clk_mgr; use it to track whether the current state has FAMS enabled; if it has, then do not disable FAMS in prepare_bandwidth, and do not set optimized_required. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets optimized_required. This change expects that Freesync requests are blocked when optimized_required is true. Reviewed-by:
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Leon Huang authored
[Why] set ABM pipe/backlight gets some issues when abm callback func pointers are NULL. For some usecase, driver would like to control PWM level before ABM resource is ready. However, recent flow refactor of ABM didn't consider that use case. [How] Rollback flow that sending inbox command to dmub directly when ABM function pointers aren't ready. Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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Srinivasan Shanmugam authored
After reading from receiver via DPCD, check & log if it supports MST, DSC & FEC Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
The previous 'commit ca9beb8a ("drm/amd/display: Add logging when setting DP sink power state fails")', it is better to unconditionally print "failed to power up sink", because we are returning DC_ERROR_UNEXPECTED. Fixes: ca9beb8a ("drm/amd/display: Add logging when setting DP sink power state fails") Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Leon Huang authored
[Why] Refactor ABM feature and implement inbox command for DMUB. [How] Implement the ioctl to send inbox command to DMUB. Reviewed-by:
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:277:6: warning: symbol 'dccg314_init' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
This commit replaces spaces with tabs in multiple functions and adjusts the indentation in some other parts of the code to improve readability. Reviewed-by:
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Rodrigo Siqueira authored
When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the required field update when using the MCLK switch. Reviewed-by:
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Rodrigo Siqueira authored
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values associated with clock speed and memory channels. Reviewed-by:
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Chong Li authored
[WHY] Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an atomic context. We shouldn't access registers through KIQ since "msleep()" may be called in "amdgpu_kiq_rreg()". [HOW] Move function "amdgpu_virt_release_full_gpu()" after function "amdgpu_device_ip_late_init()", to ensure that registers be accessed through RLCG instead of KIQ. Call Trace: <TASK> show_stack+0x52/0x69 dump_stack_lvl+0x49/0x6d dump_stack+0x10/0x18 __schedule_bug.cold+0x4f/0x6b __schedule+0x473/0x5d0 ? __wake_up_klogd.part.0+0x40/0x70 ? vprintk_emit+0xbe/0x1f0 schedule+0x68/0x110 schedule_timeout+0x87/0x160 ? timer_migration_handler+0xa0/0xa0 msleep+0x2d/0x50 amdgpu_kiq_rreg+0x18d/0x1f0 [amdgpu] amdgpu_device_rreg.part.0+0x59/0xd0 [amdgpu] amdgpu_device_rreg+0x3a/0x50 [amdgpu] amdgpu_sriov_rreg+0x3c/0xb0 [amdgpu] gfx_v10_0_set_gfx_eop_interrupt_state.constprop.0+0x16c/0x190 [amdgpu] gfx_v10_0_set_eop_interrupt_state+0xa5/0xb0 [amdgpu] amdgpu_irq_update+0x53/0x80 [amdgpu] amdgpu_irq_get+0x7c/0xb0 [amdgpu] amdgpu_fence_driver_hw_init+0x58/0x90 [amdgpu] amdgpu_device_init.cold+0x16b7/0x2022 [amdgpu] Signed-off-by:
Chong Li <chongli2@amd.com> Reviewed-by: JingWen.Chen2@amd.com Signed-off-by:
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Tom Rix authored
gcc with W=1 reports In file included from drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36: ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error: ‘pmfw_decoded_link_width’ defined but not used [-Werror=unused-const-variable=] 66 | static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:65:18: error: ‘pmfw_decoded_link_speed’ defined but not used [-Werror=unused-const-variable=] 65 | static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5}; | ^~~~~~~~~~~~~~~~~~~~~~~ These variables are defined and used in smu_v13_0_7_ppt.c and smu_v13_0_0_ppt.c. There should be only one definition. So define the variables as globals in smu_v13_0.c Signed-off-by: -
Jane Jian authored
add jpeg table size to ctx table size rather than override it Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
JingWen Chen <JingWen.Chen2@amd.com> Signed-off-by:
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- 17 Apr, 2023 1 commit
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.4-2023-04-14: amdgpu: - S4 fixes for APUs - GFX11 fixes - Misc code cleanups - DCN 3.2 fixes - DCN 3.1.4 fixes - FPO/FAMS work to improve display power savings - DP fixes - UMC 8.10 code cleanup - SDMA v4 fix - GPU clock counter fixes - SMU 13 fixes - Sdma v6 invalidation fix for preemption - RAS fixes - S0ix fix - GC 9.4.3 updates amdkfd: - Fix user pointers with IOMMU - Fix coherency flag handling Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230414204609.7942-1-alexander.deucher@amd.com
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- 14 Apr, 2023 14 commits
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Le Ma authored
Add some basic definitions and structure member. Inscrease MAX_WB slots to 1024 to support the increasing number of rings for multiple partitions. v2: unify naming style Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Le Ma authored
It looks better to place this field in ring structure. Also drop the repeated ring funcs definitions if there's no difference except for vmhub field. v2: rename the field to vm_hub like others (Le) v3: apply the changes to new ip blocks (Hawking) v4: fix vcn sw ring (Alex) Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Jane Jian authored
This reverts commit fe120b9f. This patch impacts sriov multi-vf stability Signed-off-by:
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Hawking Zhang authored
Add common IP handling for GC 9.4.3 Signed-off-by:
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Srinivasan Shanmugam authored
Log when Clock recovery is successful, as part of DP link training process. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Hawking Zhang authored
init asic funcs and cp/pg flags for GC 9.4.3 Signed-off-by:
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Hawking Zhang authored
add gfx_funcs callbacks implemenation based on gc_v9_4_3 ip headers Signed-off-by:
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Srinivasan Shanmugam authored
Log if we fail to setup sink power states. Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Graham Sider authored
Required for Thunk GFX version sysfs query. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
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Amber Lin authored
GC 9.4.3 uses the hardware to update AQL queues read pointer, so remove CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK flag from MQD if it's GC 9.4.3, and keep it for other existing gfx9 ASICs. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Li Ma authored
Reserve the MOUDLE_FIRMWARE declaration of gc_11_0_*_mes.bin to fix falling back to old mes bin on failure via autoload. Fixes: 97998b89 ("drm/amd/amdgpu: introduce gc_*_mes_2.bin v2") Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Jesse Zhang authored
Due to switch to golden tsc register to get clock counter for raven/ raven2. Chang the reference clock from 25MHZ to 100MHZ. Suggested-by:
shanshengwang <shansheng.wang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Signed-off-by:
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Aaron Liu authored
GFX is in gfxoff mode during s0ix so we shouldn't need to actually execute kfd_iommu_suspend/kfd_iommu_resume operation. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Hawking Zhang authored
all the gc v9_4_3 registers fall in gc_rlcpdec address range have different relative offsets and base_idx from the ones defined in gc v9_0 ip headers. gc_v9_0_rlc_funcs can not be reused anymore for gc v9_4_3 v2: drop unused handshake function (Alex) Signed-off-by:
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- 13 Apr, 2023 7 commits
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Daniel Vetter authored
Merge tag 'drm-intel-next-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Just one Cc:stable fix for sampler indirect state in bindless heap. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZDfxo+PXyw9ivFLI@jlahtine-mobl.ger.corp.intel.com
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Hawking Zhang authored
Was introduced as workaround. not needed anymore Signed-off-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Shashank Sharma authored
This patch adds double include protection for doorbell.h Cc: Christian Koenig <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Shashank Sharma authored
Rename doorbell.num_doorbells to doorbell.num_kernel_doorbells to make it more readable. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Acked-by:
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Jesse Zhang authored
Due to raven/raven2 maybe enable sclk slow down, they cannot get clock count by the RLC at the auto level of dpm performance. So switch to golden tsc register. Suggested-by:
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Evan Quan authored
Update the driver implementations to fit those data exposed by PMFW. Signed-off-by:
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YiPeng Chai authored
Add gfx v11_0_3 fed irq handling for sriov. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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