- 18 Jul, 2019 40 commits
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Le Ma authored
Provides the absolute offsets of the IP register blocks. v2: update chip name in source code v3: squash in MP offset updates (Alex) Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo Liu authored
VCN is the multi-media block. Signed-off-by:
Leo Liu <leo.liu@amd.com> Acked-by:
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Le Ma authored
SDMA is the system DMA block. Signed-off-by:
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Le Ma authored
mmhub is the GPU memory hub used by SDMA and VCN. Signed-off-by:
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Alex Deucher authored
It's the same as navi10. Signed-off-by: -
Alex Deucher authored
Same thing applies to navi14 as navi10. Signed-off-by: -
Jack Xiao authored
Based on navi10 gfxoff logic, enable the related code path for navi14. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Xiaojie Yuan authored
Enable VCN dynamic powergating for navi14. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
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Xiaojie Yuan authored
gfxoff doesn't work on navi14 yet, so disable it for now Signed-off-by:
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Xiaojie Yuan authored
Enable VCN power gating by default. Signed-off-by:
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Xiaojie Yuan authored
not used. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Set appropriate CG flags for navi14. Signed-off-by:
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Xiaojie Yuan authored
same as navi10. Signed-off-by:
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Xiaojie Yuan authored
same as navi10. Signed-off-by:
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Xiaojie Yuan authored
So the dependency gets properly tracked. Signed-off-by:
Snow Zhang <snow.zhang@amd.com> Reviewed-by:
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James Zhu authored
Add navi14 vcn firmware, and enable VCN on navi14. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Xiaojie Yuan authored
not needed for navi14 at the moment. Signed-off-by:
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Xiaojie Yuan authored
Not relevant on navi14. Signed-off-by:
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Bhawanpreet Lakha authored
Add revs for navi10 and 14. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
enable DC for navi14. Signed-off-by:
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Bhawanpreet Lakha authored
Change the pipes to 5 if the asic is nv14 This is a temp patch, there was some refactor in the dml part of the code. which is not in this branch. for now this is good, we can implement this properly once we have an updated branch. Signed-off-by:
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Bhawanpreet Lakha authored
Mostly shared with navi10. Signed-off-by:
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Xiaojie Yuan authored
same as navi10. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Update for navi14. Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. v2: squash in logic fix (Colin Ian King) v3: squash in logic simplification (Alex) Signed-off-by:
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Xiaojie Yuan authored
Virtual display is a sw based kms interface for virtualization and emulation. Signed-off-by:
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Xiaojie Yuan authored
Add the initial IP blocks for navi14 Signed-off-by:
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Xiaojie Yuan authored
same as navi10 Signed-off-by:
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Jack Xiao authored
max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by:
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Tao Zhou authored
Updated settings from hw team. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
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Xiaojie Yuan authored
Add updated settings from hw team. Signed-off-by:
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Xiaojie Yuan authored
Updated settings for hw team. Signed-off-by:
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Xiaojie Yuan authored
Add golden settings for navi14. Signed-off-by:
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Xiaojie Yuan authored
Needed for clockgating. Signed-off-by:
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Xiaojie Yuan authored
Update settings for navi14. Signed-off-by:
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Xiaojie Yuan authored
Same as navi10. Signed-off-by:
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Xiaojie Yuan authored
Add navi14 to appropriate cases. Signed-off-by:
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