- 03 Sep, 2020 7 commits
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Alex Deucher authored
Need to read back from registers for manual mode rather than using the metrics table. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1164Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Will be used to fetch the fan speeds when manual fan mode is set. v2: squash in a Coverity fix from Colin Ian King Reviewed-by:
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Alex Deucher authored
No longer needed as we can calculate it based on the fan's max rpm. v2: minor code rework Reviewed-by:
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Alex Deucher authored
No longer needed as we can calculate it based on the fan's max rpm. v2: rework code to avoid possible uninitialized variable use. Reviewed-by:
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Alex Deucher authored
grab the value from the pptable. Reviewed-by:
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Alex Deucher authored
To fetch the max rpm from pptable. Reviewed-by:
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Nirmoy Das authored
On hardware with multiple uvd instances, dependent uvd jobs may get scheduled to different uvd instances. Because uvd_enc jobs retain hw context, dependent jobs should always run on the same uvd instance. This patch disables GPU scheduler's load balancer for a context that binds jobs from the same context to a uvd instance. v2: Squash in uvd_enc fix Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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- 31 Aug, 2020 2 commits
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Mukul Joshi authored
Replace spaces with Tabs to fix indentation in kfd_smi_event enum. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Mukul Joshi authored
Add support for reporting GPU reset events through SMI. KFD would report both pre and post GPU reset events. Signed-off-by:
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- 28 Aug, 2020 1 commit
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Nirmoy Das authored
Fixes below compiler warnings: CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration] 381 | void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags) | ^~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘inline’ is not at beginning of declaration [-Wold-style-declaration] drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function ‘amdgpu_device_fini’: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3381:6: warning: variable ‘r’ set but not used [-Wunused-but-set-variable] 3381 | int r; | ^ Signed-off-by:
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- 27 Aug, 2020 8 commits
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Kai-Heng Feng authored
Commit 2e26ccb1 ("drm/radeon: prefer lower reference dividers") fixed screen flicker for HP Compaq nx9420 but breaks other laptops like Asus X50SL. Turns out we also need to favor lower feedback dividers. Users confirmed this change fixes the regression and doesn't regress the original fix. Fixes: 2e26ccb1 ("drm/radeon: prefer lower reference dividers") BugLink: https://bugs.launchpad.net/bugs/1791312 BugLink: https://bugs.launchpad.net/bugs/1861554Reviewed-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Sandeep Raghuraman authored
On my R9 390, the voltage was reported as a constant 1000 mV. This was due to a bug in smu7_hwmgr.c, in the smu7_read_sensor() function, where some magic constants were used in a condition, to determine whether the voltage should be read from PLANE2_VID or PLANE1_VID. The VDDC mask was incorrectly used, instead of the VDDGFX mask. This patch changes the code to use the correct defined constants (and apply the correct bitshift), thus resulting in correct voltage reporting. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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Sandeep Raghuraman authored
Starting in Linux 5.8, the graphics and memory clock frequency were not being reported for CIK cards. This is a regression, since they were reported correctly in Linux 5.7. After investigation, I discovered that the smum_send_msg_to_smc() function, attempts to call the corresponding get_argument() function of ci_smu_funcs. However, the get_argument() function is not defined in ci_smu_funcs. This patch fixes the bug by specifying the correct get_argument() function. Fixes: a0ec2256 ("drm/amd/powerplay: unified interfaces for message issuing and response checking") Signed-off-by:
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Jiansong Chen authored
Enable MP0 clock DPM for sienna_cichlid. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Jiawei authored
Optimize code to iterate less loops in amdgpu_device_ip_reinit_early_sriov() Signed-off-by:
Jiawei <Jiawei.Gu@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
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Evan Quan authored
Suppress the warning below: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.c:274 phm_check_smc_update_required_for_display_configuration() warn: signedness bug returning '(-22)' Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Evan Quan authored
Normally softwareshutdowntemp should be greater than Thotspotlimit. However, on some VEGA10 ASIC, the softwareshutdowntemp is 91C while Thotspotlimit is 105C. This seems not right and may trigger some false alarms. Signed-off-by:
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Kevin Wang authored
v1: the C type "unsigned long" size is 32bit on 32bit system, it will cause code logic error, so replace it with "uint64_t". v2: remove duplicate cast operation. Signed-off-by:
Kevin <kevin1.wang@amd.com> Suggest-by:
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- 26 Aug, 2020 22 commits
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Guchun Chen authored
When resetting EDC related register, all CUs needs to be visited, otherwise, garbage data from EDC register of missed SEs would present. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Dinghao Liu authored
When amdgpu_display_modeset_create_props() fails, state and state->context should be freed to prevent memleak. It's the same when amdgpu_dm_audio_init() fails. Signed-off-by:
Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by:
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Jiansong Chen authored
Disable runtime pm for navy_flounder temporarily. Signed-off-by:
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Wayne Lin authored
[Why] In dm_dp_aux_transfer() now, we forget to handle AUX_WR fail cases. We suppose every write wil get done successfully and hence some AUX commands might not sent out indeed. [How] Check if AUX_WR success. If not, retry it. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Alex Deucher authored
The values for "se_num" and "sh_num" come from the user in the ioctl. They can be in the 0-255 range but if they're more than AMDGPU_GFX_MAX_SE (4) or AMDGPU_GFX_MAX_SH_PER_SE (2) then it results in an out of bounds read. Reported-by:
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Alex Deucher authored
Virtual display is non-atomic so report false to avoid checking atomic state and other atomic things at runtime. v2: squash into the sr-iov check Acked-by:
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Nicholas Kazlauskas authored
[Why] DC uses these to raise the voltage as needed for higher dispclk/dppclk and to ensure that we have enough bandwidth to drive the displays. There's a bug preventing these from actuially sending messages since it's checking the actual clock (which is 0) instead of the incoming clock (which shouldn't be 0) when deciding to send the hardmin. [How] Check the clocks != 0 instead of the actual clocks. Fixes: 9ed9203c ("drm/amd/powerplay: rv dal-pplib interface refactor powerplay part") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Jiansong Chen authored
Switch default gpu reset method to MODE1 for navy_flounder. Signed-off-by:
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Stanley.Yang authored
The ctx->features are new RAS implementation which is only available for Vega20 and onwards, it is not available for vega10, vega10 should follow legacy ECC implementation. Changed from V1: wrap function to initialize kfd node properties Changed from V2: remove wrap function and SDMA SRAM ECC check Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Evan Quan authored
Do the maths in celsius degree. This can fix the issues caused by the changes below: drm/amd/pm: correct Vega20 swctf limit setting drm/amd/pm: correct Vega12 swctf limit setting drm/amd/pm: correct Vega10 swctf limit setting Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Tao Zhou authored
asd is not ready for some ASICs in early stage, and psp->asd_fw is more generic than ASIC name in the check. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Alex Dewar authored
Issue identified with Coccinelle. Signed-off-by:
Alex Dewar <alex.dewar90@gmail.com> Signed-off-by:
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Alex Deucher authored
This allows us to add asic specific workarounds for atom asic init while keeping the adev specifics out of the atombios parser code. Acked-by:
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Alex Deucher authored
Nothing to do for this family. Acked-by:
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Alex Deucher authored
We need to restore some registers prior to running asic init to work around a firmware bug. Acked-by:
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Alex Deucher authored
Nothing to do for this family. Acked-by:
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Alex Deucher authored
Nothing to do for this family. Acked-by:
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Alex Deucher authored
Nothing to do for this family. Acked-by:
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Alex Deucher authored
This callback can be used by asics that need to do something special prior to calling atom asic init. Acked-by:
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Alex Deucher authored
Properly define this register using a relative offset rather than an absolute offset and use the proper SOC15 macros to access it. It's also DCN, not DCE, so remove it from the DCE12 header. No functional change. Acked-by:
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Bhawanpreet Lakha authored
dpcs reg are missing for dcn3 link encoder regs list, so add them. Also remove DPCSTX_DEBUG_CONFIG and RDPCSTX_DEBUG_CONFIG as they are unused and cause compile errors for dcn3 Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Felix Kuehling authored
No need to use a function pointer because the implementation is not ASIC-specific. Signed-off-by:
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