- 23 May, 2014 9 commits
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Geert Uytterhoeven authored
- Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Heiko Stuebner authored
From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by:
Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Acked-by:
Tomasz Figa <t.figa@samsung.com> Acked-by:
Max Schwarz <max.schwarz@online.de> Tested-by:
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Ulrich Hecht authored
Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
Geert Uytterhoeven <geert@linux-m68k.org> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Andrew Bresticker authored
Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by:
Jim Lin <jilin@nvidia.com> Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
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Andrew Bresticker authored
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by:
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Jim Lin authored
The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by:
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Jim Lin authored
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by:
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Anders Berg authored
Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by:
Anders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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Laurent Pinchart authored
The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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- 22 May, 2014 1 commit
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Sylwester Nawrocki authored
This patch adds of_clk_get_by_clkspec() helper function, which does only a struct clk lookup from the clock providers. It is used in the subsequent patch where parsing of a clock from device tree and the lookup from providers needed to be split. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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- 21 May, 2014 2 commits
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Linus Walleij authored
The IM-PD1 PrimeCells all have pclk assignments though this clock cannot be controlled, and we need to provide this as a dummy clock for the PL061 GPIO driver to probe, so let's assign it to all the cells on the board. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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git://git.xilinx.com/linux-xlnxMike Turquette authored
arm: Xilinx Zynq clk patches for v3.16 - Keep debug clocks in bootup state - Fix email address in si570
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- 20 May, 2014 1 commit
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Michal Simek authored
Just fix missing ">" in the email. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
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- 16 May, 2014 3 commits
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Stephen Boyd authored
When consolidating the msm8660 GCC probe code I forgot to keep around these temporary clock registrations. Put them back so the clock tree is not entirely orphaned. Fixes: 49fc825f (clk: qcom: Consolidate common probe code) Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Mike Turquette authored
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Tuomas Tynkkynen authored
The value written to PLLE_AUX was incorrect due to a wrong variable being used. Without this fix SATA does not work. Cc: stable@vger.kernel.org Signed-off-by:
Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by:
Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Tested-by:
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- 15 May, 2014 3 commits
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Fabio Estevam authored
Remove the 'gpios' property from the documentation as this is something that the current fixed clock driver does not handle. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Arnd Bergmann authored
The impd1 code on mach-integrator can be a loadable module, so we have to export icst_clk_register, integrator_impd1_clk_init and integrator_impd1_clk_exit. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
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Mike Turquette authored
Merge tag 'clk-hisi-for-v3.16' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon enable hix5hd2 clock
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- 14 May, 2014 1 commit
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Hans de Goede authored
__clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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- 13 May, 2014 7 commits
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git://git.infradead.org/linux-mvebuMike Turquette authored
clk mvebu changes for v3.16 - orion5x: brand new driver
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Simon Horman authored
Add MSTP clock support for the r8a7779 SoC The only change required appears to be to note a new compatibility string in the bindings. Cc: devicetree@vger.kernel.org Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Simon Horman authored
The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by:
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Mike Turquette authored
Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga Adds support getting the divider registers for the MAIN PLL that was once thought to be hidden.
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Geert Uytterhoeven authored
Improve the wording for the clock-indices binding documentation. Also replace "empty nodes" by "empty strings", as reported before by Sergei Shtylyov. Signed-off-by:
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Geert Uytterhoeven authored
General: - Add parameter names to .round_rate() and .set_rate(). Documentation/clk.txt: - Add missing parameter for .set_rate(), - Add missing .debug_init(). include/linux/clk-provider.h: - Add parent rate documentation for .round_rate(), - Reorder documentation to match implementation order, - Add missing documentation for .init(). Signed-off-by:
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Geert Uytterhoeven authored
- Remove spaces in front of TABs, - Correct indentation for some CLK_* flag descriptions. Signed-off-by:
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- 12 May, 2014 6 commits
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Mike Turquette authored
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Ben Dooks authored
With the addition of clock-indices, we need to change the renesas clock implementation to use these instead of the local definition of "renesas,clock-indices". Since this will break booting with older device trees, we add a simple auto-detection of which properties are present. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Acked-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Dinh Nguyen authored
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by:Dinh Nguyen <dinguyen@altera.com>
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Zhangfei Gao authored
Signed-off-by:
Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org>
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Zhangfei Gao authored
Add hisi_clk_register_gate register clk gate table Signed-off-by:
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Zhangfei Gao authored
Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by:
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- 05 May, 2014 2 commits
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Emilio López authored
HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by:
Emilio López <emilio@elopez.com.ar> Signed-off-by:
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Emilio López authored
This commit implements .determine_rate, so that our factor clocks can be reparented when needed. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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- 30 Apr, 2014 5 commits
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Kumar Gala authored
* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs * Fix incorrect offset for PMIC_SSBI2_RESET * Fix typo: SIC_TIC -> SPS_TIC_H SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK * Fix naming convention: SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK SATA_SRC_CLK -> SATA_CLK_SRC Signed-off-by:
Kumar Gala <galak@codeaurora.org> Reviewed-by:
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Kumar Gala authored
The APQ8064 and MSM8960 share a significant amount of clock data and code between the two SoCs. Rather than duplicating the data we just add support for a unqiue APQ8064 clock table into the MSM8960 code. For now add just enough clocks to get a basic serial port going on an APQ8064 device. Signed-off-by:
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Stephen Boyd authored
Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by:
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Stephen Boyd authored
This simplifies error paths in drivers that use optional clocks by allowing the NULL or error pointer to be passed unconditionally. Signed-off-by:
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Stephen Boyd authored
The same if-else statement exists four times to recalculate the rate of a clock. Consolidate this logic into a single function to save some lines. Signed-off-by:
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