- 26 Sep, 2023 40 commits
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Rodrigo Siqueira authored
bios_parser2 uses space instead of tabs in multiple areas; this commit converts those spaces into tabs. It also removes some other small details. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Hung authored
[WHY] edid_override and drm_edid_override_connector_update, according to drm documentation, should not be referred outside drm_edid. [HOW] Remove and replace them accordingly. This can tested by IGT's kms_hdmi_inject test. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Hamza Mahfooz authored
For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Alex Hung authored
[WHY & HOW] IGT's kms_hdmi_inject (subtest inject_audio) triggers a warning message from dce_aud_az_configure. This can be fixed by checking Virtual signal that does not need to configure AZ audio since it does not have any. Reviewed-by:
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Ma Jun authored
Add reset option for fan_curve. User can use command "echo r > fan_cure" to reset the fan_curve to boot value Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This change adds a method to block mpo when it would cause us to exit pstate support. We should block mpo by default where MPO causes issues by preventing pstate change. Reviewed-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] Triggering OTG sync before all OTG/HPO clock programming is complete causes timing sync to fail and a subsequent P-state hang. [How] Move DTB clock programming earlier in the sequence to enable_stream_timing. Reviewed-by:
Ariel Bernstein <eric.bernstein@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Duncan Ma authored
[Why] There is a race condition between x86 and dmcub fw when attempting to exit IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This can cause unexpected hang when DMCUB attempt to exit while PMFW still tries to enter IPS2. [How] A new design has been introduced to remove race conditions and improve the handshake between x86 and DMCUB. An AON scratch register is borrowed from PMFW to determine whether DMCUB has committed to IPS entry or not. In the case when dmcub has committed IPS entry, x86 must poll until an exit event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait upperbound of evaluation and IPS entry time to ensure IPS2 exit event has been sent to PMFW. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Wenjing Liu authored
[why] With the more generic hw minimal state transition sequence, this limitation has been overcome. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] We do not have a programming sequence to support seamless transition between MPC combine to ODM combine when plane count remains the same. This can happen with windowed MPO ODM use cases when plane scaling is changed over ODM Combine's capability. [How] We are adding a programming sequence specifically to handle the transition between MPC combine and ODM combine during plane scaling change. Reviewed-by:
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Wenjing Liu authored
[why] ODM combine could prevent us from supporting more planes we will reset ODM slice count back to 1 when all planes have been removed to maximize the amount of planes supported when new planes are added. [how] reset ODM slice count when all planes are removed. Reviewed-by:
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Wenjing Liu authored
[why] commit minimal transition state would update current state to new state with surface and stream update applied. If we determine fast update only after we have committed the minimal transition state based on new state, we will skip committing the full new state. [how] determine fast update only earlier based on the actaul currents state. Only skip full commit when the transition between actual current state and new state is fast update only. Reviewed-by:
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Qingqing Zhuo authored
[Why & How] mmhub_reg_offsets never used in code. Remove it. Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Xiaogang Chen authored
This patch fixes: 1: ref number of prange's svm_bo got decreased by an async call from hmm. When wait svm_bo of prange got released we shoul also wait prang->svm_bo become NULL, otherwise prange->svm_bo may be set to null after allocate new vram buffer. 2: During waiting svm_bo of prange got released in a while loop should reschedule current task to give other tasks oppotunity to run, specially the the workque task that handles svm_bo ref release, otherwise we may enter to softlock. Signed-off-by:
Xiaogang.Chen <xiaogang.chen@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
Otherwise GPU may access the stale mapping and generate IOMMU IO_PAGE_FAULT. Move this to inside p->mutex to prevent multiple threads mapping and unmapping concurrently race condition. After kfd_mem_dmaunmap_attachment is removed from unmap_bo_from_gpuvm, kfd_mem_dmaunmap_attachment is called if failed to map to GPUs, and before free the mem attachment in case failed to unmap from GPUs. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Christian König authored
For the PASID flushing we already handled that at a higher layer, apply those workarounds to the standard flush as well. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
Instead of each implementation doing this more or less correctly move taking the reset lock at a higher level. v2: fix typo Signed-off-by:
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Christian König authored
That function never fails, drop the error return. Signed-off-by:
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Christian König authored
The same PASID can be used by more than one VMID, reset each of them. Use the common KIQ handling. Signed-off-by:
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Christian König authored
The same PASID can be used by more than one VMID, reset each of them. Use the common KIQ handling. Signed-off-by:
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Christian König authored
Testing for reset is pointless since the reset can start right after the test. The same PASID can be used by more than one VMID, invalidate each of them. Move the KIQ and all the workaround handling into common GMC code. Signed-off-by:
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Christian König authored
Testing for reset is pointless since the reset can start right after the test. Grab the reset semaphore instead. The same PASID can be used by more than once VMID, build a mask of VMIDs to invalidate instead of just restting the first one. Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Acked-by:
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Christian König authored
Testing for reset is pointless since the reset can start right after the test. Grab the reset semaphore instead. The same PASID can be used by more than once VMID, build a mask of VMIDs to invalidate instead of just restting the first one. Signed-off-by:
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Christian König authored
Remove leftovers from copying this from the gmc v10 code. v2: squash in fix from Yifan Signed-off-by:
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Christian König authored
Move the SDMA workaround necessary for Navi 1x into a higher layer. v2: use dev_err Signed-off-by:
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Tao Zhou authored
The amdgpu_ras_eeprom_control.bad_channel_bitmap is u32 type, but the channel index could be larger than 32. For the ASICs whose channel number is more than 32, the amdgpu_dpm_send_hbm_bad_channel_flag interface is not supported, so we simply bypass channel bitmap update under this condition. v2: replace sizeof with BITS_PER_TYPE, we should check bit number instead of byte number. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Prepare for bad page retirement. Signed-off-by:
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Kenneth Feng authored
add unique_id for gc 11.0.3 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Alex Deucher authored
Fixes a few style issues: - Only calculate the dto_params and dp_hpo_inst when dccg is present. - Fix indentation - Drop empty else block Fixes: 7f7925e2 ("drm/amd/display: Fix MST recognizes connected displays as one") Cc: Muhammad Ahmed <ahmed.ahmed@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Philip Yang authored
If retry cam enabled, we don't use sw retry fault filter and add fault into sw filter ring, so we shouldn't remove fault from sw filter. Signed-off-by:
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Christian König authored
The KIQ code path was ignoring the second flush. Also avoid long lines and re-calculating the register offsets over and over again. Signed-off-by:
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Swarup Laxman Kotiaklapudi authored
Fix kernel-doc warnings discovered in AMD gpu display driver. Fixes these warnings: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'overlap_only' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_gain_mode' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'background_color_bpc' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'top_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_inside_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_outside_gain' not described in 'mpcc_blnd_cfg'. Tested-by:
Randy Dunlap <rdunlap@infradead.org> Acked-by:
Swarup Laxman Kotiaklapudi <swarupkotikalapudi@gmail.com> Signed-off-by:
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Philip Yang authored
On GFX v9.4.3 dGPU, applications have random timeout failure when XNACK on, dmesg log has "amdgpu: IH soft ring buffer overflow 0x900, 0x900", because dGPU mode has 272 cam entries. After increasing IH soft ring to 512 entries, no more IH soft ring overflow message and application passed. Fixes: bf80d34b ("drm/amdgpu: Increase soft IH ring size") Signed-off-by:
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Lijo Lazar authored
On a full device reset, PSP FW gets unloaded. Hence restore the partition mode by placing a new request. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following: - Use optc32 instead of optc30 in DC - Optimize OLED T7 delay - Multiple fixes for MST, register mas, and others - Update driver and IPS interop - Improve z8 watermark mask - DCN35 updates - Enable replay for DCN35 - Temporarily disable clock gating Tested-by:
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Rodrigo Siqueira authored
There are multiple parts of the code that DC does not use anymore, and this commit drops those dead codes. Tested-by:
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Muhammad Ahmed authored
Enable DCN low mem power by default. Tested-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
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Muhammad Ahmed authored
Update with extended blank Vstartup adjustment for replay. Tested-by:
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Ovidiu Bunea authored
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET. REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 in some specific HDMI configurations. Tested-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by:
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Agustin Gutierrez authored
[Why] Driver doesn't need T7 delay for OLED panels, since it doesn't control power sequence. [How] This delay can be skipped to optimize resume times. Tested-by:
Swapnil Patel <swapnil.patel@amd.com> Acked-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
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