- 29 Mar, 2021 1 commit
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
Conversion of misc display DT bindings to YAML Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/YFgOFL/yMUkyxqK3@pendragon.ideasonboard.com
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- 26 Mar, 2021 1 commit
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Daniel Vetter authored
Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.13-2021-03-23: amdgpu: - Debugfs cleanup - Various cleanups and spelling fixes - Flexible array cleanups - Initial AMD Freesync HDMI - Display fixes - 10bpc dithering improvements - Display ASSR support - Clean up and unify powerplay and swsmu interfaces - Vangogh fixes - Add SMU gfx busy queues for RV/PCO - PCIE DPM fixes - S0ix fixes - GPU metrics data fixes - DCN secure display support - Backlight type override - Add initial support for Aldebaran - RAS fixes - Prime fixes for A+A systems - Reset fixes - Initial resource cursor support - Drop legacy IO BAR requirements - Various power fixes amdkfd: - MMU notifier fixes - APU fixes radeon: - Debugfs cleanups - Flexible array cleanups UAPI: - amdgpu: Add a new INFO ioctl interface to query video capabilities rather than hardcoding them in userspace. This allows us to provide fine grained asic capabilities (e.g., if a particular part is bandwidth limited, we can limit the capabilities). Proposed userspace: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps - amdkfd: bump the driver version. There was a problem with reporting some RAS features on older versions of the driver. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21 Danvet: A bunch of conflicts all over, but it seems to compile ... I did put the call to dc_allow_idle_optimizations() on a single line since it looked a bit too jarring to be left alone. Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com
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- 24 Mar, 2021 38 commits
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Felix Kuehling authored
Indicate the availability reliable SRAM EDC state in the new bit in the device properties. Proposed userspace changes: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Felix Kuehling authored
The HW is not in production yet. Driver support is still in development. Signed-off-by:
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Christian König authored
As noted during the review this approach doesn't make sense at all. We should not apply any limitation on the VRAM applications can use inside the kernel. If an application or end user wants to reserve a certain amount of VRAM for bad pages handling we should do this in the upper layer. This reverts commit f89b881c. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Christian König authored
We are seeing VM page faults with this. Revert the change until the bugs are fixed. This reverts commit 94ae8dc5. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
Move the function protoype to the right header and guard the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available with DCN. Fixes: 8c2f14c3 ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c:220:65-70: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:721:65-70: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:1139:67-72: WARNING: conversion to bool not needed here. Reported-by:
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xinhui pan authored
drm_gem_object_put() should be paired with drm_gem_object_lookup(). All gem objs are saved in fb->base.obj[]. Need put the old first before assign a new obj. Trigger VRAM leak by running command below $ service gdm restart Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Acked-by:
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Chen Li authored
kvmalloc_array + __GFP_ZERO is the same with kvcalloc. As for p->chunks, it will be used in: ``` if (ib_chunk->kdata) memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); ``` If chunks doesn't zero out with __GFP_ZERO, it may point to somewhere else, e.g., ``` Unable to handle kernel paging request at virtual address 0000000000010000 ... pc is at memcpy+0x84/0x250 ra is at radeon_cs_ioctl+0x368/0xb90 [radeon] ``` after allocating chunks with __GFP_KERNEL/kvcalloc, this bug is fixed. Fixes: 3fcb4f01 ("drm/radeon: Use kvmalloc for CS chunks") Reviewed-by:
Chen Li <chenli@uniontech.com> Signed-off-by:
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Alex Deucher authored
We set the same variable a few lines above. Drop the duplicate setting. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] Find out that when we are registering vertical interrupt0, we get DC_IRQ_SOURCE_INVALID when call dc_interrupt_to_irq_source for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL. After analyzing, it's due to the defined value for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL is not (DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL + 1). It's not incremental sequence. [How] Use an array to record all vertical interrupt0 SRCID. While registering interrupt, use an incremental index to visit the array to get the right SRCID to register. Also add error handling to avoid potential pointer problem. Signed-off-by:
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Evan Quan authored
For V1_0 and V1_1, they come with different size. Misuse may cause out of memory access. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Nikola Cornij authored
Since this is a "revert of a revert", the end effect is that freesync video is back to its original state, the way it was before the first revert. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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shaoyunl authored
With arg 1 BACO reset, it will try to reload the SMU FW after reset. This might failed if driver already in a pending reset status during probe period. Arg 0 reset will bring asic back to a clean state and driver will re-init everythign including SMU FW Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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shaoyunl authored
SMU internal might need to check this pending_reset setting to decide the reset method Signed-off-by:
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shaoyunl authored
This is to fix the case where it only enable the light SMU on normal device init. This feature actually need to be enabled after ASIC been reset as well. Signed-off-by:
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Qingqing Zhuo authored
[Why] vblank_workqueue is never released. [How] Free it upon dm finish. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
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Yao Wang1 authored
[Why] When driver disabled, we driver force the YCbCr420 to RGB, which means some register will be changed, such as RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0 When driver re-enabled, OS will Set Mode YCbCr420 again, which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV should to be 1 again, but dmub fw can’t update the register to 1 due to the mpll is not off [How] Adds an interface to disable accelerated mode bit, which allows DM to decide to call during driver disable/unload scenarios. Tested-by:
Yao Wang1 <Yao.Wang1@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Dmytro Laktyushkin authored
SOC needs to be updated to the WM set A values before validation happens. Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Incorrect variable used, missing initialization during validation. Tested-by:
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Aric Cyr authored
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add debug out when viewport too small * use max lb for latency hiding * System black screen hangs on driver load * Fix UBSAN warning for not a valid value for type '_Bool' * Fix for outbox1 ring buffer typecasting issue * Bypass sink detect when there are no eDPs connected * Increase precision for bpp in DSC calculations * Add changes for dsc bpp in 16ths and unify bw calculations * Correct algorithm for reversed gamma * Remove MPC gamut remap logic for DCN30 * Fix typo for helpers function name * Fix secure display lock problems * Fix no previous prototype warning * Separate caps for maximum RGB and YUV plane counts * Add debugfs to control DMUB trace buffer events * [FW Promotion] Release 0.0.56 * DCHUB underflow counter increasing in some scenarios * fix dml prefetch validation * fix dcn3+ bw validation soc param update sequence * add a func to disable accelerated mode * Fix potential memory leak Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Aric Cyr authored
[Why] When unplugging a display, the underflow counter can be seen to increase because PSTATE switch is allowed even when some planes are not blanked. [How] Check that all planes are not active instead of all streams before allowing PSTATE change. Tested-by:
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Anthony Koo authored
More updates to the comments to better describe the function of different cmds and parameters in the dmub interface. Tested-by:
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Leo (Hanghong) Ma authored
[Why] We want to have a debugfs interface to enable or disable DMCUB trace buffer events. [How] Add debugfs interface to enable or disable trace buffer events. Tested-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
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Atufa Khan authored
Not all ASICs have same plane capabilities so need to split them out for proper support handling. Tested-by:
Atufa Khan <Atufa.Khan@amd.com> Reviewed-by:
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Wayne Lin authored
[Why] Received compiling warning: All warnings (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5574:5: warning: no previous prototype for 'amdgpu_dm_crtc_late_register' [-Wmissing-prototypes] 5574 | int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'dm_update_mst_vcpi_slots_for_dsc': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6405:46: warning: variable 'old_con_state' set but not used [-Wunused-but-set-variable] 6405 | struct drm_connector_state *new_con_state, *old_con_state; | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'amdgpu_dm_commit_cursors': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8006:44: warning: variable 'new_plane_state' set but not used [-Wunused-but-set-variable] 8006 | struct drm_plane_state *old_plane_state, *new_plane_state; | ^~~~~~~~~~~~~~~ vim +/amdgpu_dm_crtc_late_register +5574 drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c 5572 5573 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY > 5574 int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 5575 { 5576 crtc_debugfs_init(crtc); 5577 5578 return 0; 5579 } 5580 #endif 5581 [How] Fix it with declaration as "static" Tested-by:kernel test robot <lkp@intel.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Wayne Lin authored
[Why] Find out few locks problems while doing secure display. They are following few parts: 1. crc_rd_work_lock in amdgpu_dm_crtc_handle_crc_window_irq() should also use spin_lock_irqsave instead of spin_lock_irq. 2. In crc_win_update_set(), crc_rd_work_lock should be grabbed after obtaining lock event_lock. Otherwise, will cause deadlock by conflicting the lock order in amdgpu_dm_crtc_handle_crc_window_irq() 3. flush_work() in crc_win_update_set() is no need and will cause deadlock since amdgpu_dm_crtc_notify_ta_to_read() also tries to grab lock crc_rd_work_lock. [How] Fix above problems. Tested-by:
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Leo (Hanghong) Ma authored
[why] Word "helper" was misspelled as "helpes" in dm_helpes_dmub_outbox0_interrupt_control function. [how] Fix the spelling. Tested-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Dillon Varone authored
[Why?] Should only reroute gamut remap to mpc unless 3D LUT is not used and all planes are using the same src->dest. [How?] Remove DCN30 specific logic for rerouting gamut remap to mpc. Tested-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Calvin Hou authored
[Why] DCN30 needs to correctly program reversed gamma curve, which DCN20 already has. Also needs to fix a bug that 252-255 values are clipped. [How] Apply two fixes into DCN30. Tested-by:
Calvin Hou <Calvin.Hou@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Vladimir Stempen <Vladimir.Stempen@amd.com> Signed-off-by:
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Dillon Varone authored
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing. [How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c. Tested-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Jun Lei authored
[Why?] Many DSC variables and related functions use whole bits for bpp. [How?] Change variables and related functions to use 16ths of a bit for bpp. Tested-by:
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Jake Wang authored
[How & Why] Check DC config to determine if there are any eDPs connected. If there are no eDPs connected, bypass sink detect when querying eDP presence. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Meenakshikumar Somasundaram authored
[WHY] Compiler warning "pointer to integer of different size" reported on outbox1 ring buffer address typecasting. Reported-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
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Anson Jacob authored
[Why] dc_cursor_position do not initialise position.translate_by_source when crtc or plane->state->fb is NULL. UBSAN caught this error in dce110_set_cursor_position, as the value was garbage. [How] Initialise dc_cursor_position structure elements to 0 in handle_cursor_update before calling get_cursor_position. Tested-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Anson Jacob <Anson.Jacob@amd.com> Reviewed-by:
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Aric Cyr authored
This reverts commit dbc43d5f as it causes crash on driver load in some scenarios. Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Enable max memory lb config to improve stutter efficiency and latency hiding. Also increase max number of lb lines to be used by dml since experiments have shown that there isnt a hard max beyond what fits in lb. Tested-by:
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