* Amlogic GXBB AO Clock and Reset Unit

The Amlogic GXBB AO clock controller generates and supplies clock to various
controllers within the Always-On part of the SoC.

Required Properties:

- compatible: value should be different for each SoC family as :
	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
	- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
	followed by the common "amlogic,meson-gx-aoclkc"
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
  * "xtal"     : the platform xtal
  * "mpeg-clk" : the main clock controller mother clock (aka clk81)
  * "ext-32k-0"  : external 32kHz reference #0 if any (optional)
  * "ext-32k-1"  : external 32kHz reference #1 if any (optional - gx only)
  * "ext-32k-2"  : external 32kHz reference #2 if any (optional - gx only)

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
used in device tree sources.

- #reset-cells: should be 1.

Each reset is assigned an identifier and client nodes can use this identifier
to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.

Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.

Example: AO Clock controller node:

ao_sysctrl: sys-ctrl@0 {
	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
	reg =  <0x0 0x0 0x0 0x100>;

	clkc_AO: clock-controller {
		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
		#clock-cells = <1>;
		#reset-cells = <1>;
		clocks = <&xtal>, <&clkc CLKID_CLK81>;
		clock-names = "xtal", "mpeg-clk";
	};

Example: UART controller node that consumes the clock and reset generated
  by the clock controller:

	uart_AO: serial@4c0 {
		compatible = "amlogic,meson-uart";
		reg = <0x4c0 0x14>;
		interrupts = <0 90 1>;
		clocks = <&clkc_AO CLKID_AO_UART1>;
		resets = <&clkc_AO RESET_AO_UART1>;
	};
