TI Keystone PCIe interface

Keystone PCI host Controller is based on the Synopsys DesignWare PCI
hardware version 3.65.  It shares common functions with the PCIe DesignWare
core driver and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt

Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
for the details of DesignWare DT bindings.  Additional properties are
described here as well as properties that are not applicable.

Required Properties:-

compatibility: "ti,keystone-pcie"
reg:	index 1 is the base address and length of DW application registers.
	index 2 is the base address and length of PCI device ID register.

pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
	interrupt-cells: should be set to 1
	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines

 Example:
	pcie_msi_intc: msi-interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	};

pcie_intc: Interrupt controller device node for Legacy IRQ chip
	interrupt-cells: should be set to 1

 Example:
	pcie_intc: legacy-interrupt-controller {
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	};

Optional properties:-
	phys: phandle to generic Keystone SerDes PHY for PCI
	phy-names: name of the generic Keystone SerDes PHY for PCI
	  - If boot loader already does PCI link establishment, then phys and
	    phy-names shouldn't be present.
	interrupts: platform interrupt for error interrupts.

DesignWare DT Properties not applicable for Keystone PCI

1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
