• Suresh Siddha's avatar
    x86, x2apic: cleanup the IO-APIC level migration with interrupt-remapping · 0280f7c4
    Suresh Siddha authored
    Impact: simplification
    
    In the current code, for level triggered migration, we need to modify the
    io-apic RTE with the update vector information, along with modifying interrupt
    remapping table entry(IRTE) with vector and destination. This is to ensure that
    remote IRR bit inthe IOAPIC RTE gets cleared when the cpu does EOI.
    
    With this patch, for level triggered, we eliminate the io-apic RTE modification
    (with the updated vector information), by using a virtual vector (io-apic pin
    number).  Real vector that is used for interrupting cpu will be coming from
    the interrupt-remapping table entry. Trigger mode in the IRTE will always be
    edge, and the actual level or edge trigger will be setup in the IO-APIC RTE.
    So a level triggered interrupt will appear as an edge to the local apic
    cpu but still as level to the IO-APIC.
    
    With this change, level irq migration can be done by simply modifying
    the interrupt-remapping table entry with out changing the io-apic RTE.
    And as the interrupt appears as edge at the cpu, in addition to do the
    local apic EOI, we need to do IO-APIC directed EOI to clear the remote
    IRR bit in  the IO-APIC RTE.
    
    This simplies the irq migration in the presence of interrupt-remapping.
    Idea-by: default avatarRajesh Sankaran <rajesh.sankaran@intel.com>
    Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
    Cc: Eric W. Biederman <ebiederm@xmission.com>
    Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
    0280f7c4
io_apic.c 97.8 KB