• Stephan Günther's avatar
    scsi: mpt3sas: fix memory ordering on 64bit writes · 23c3828a
    Stephan Günther authored
    With commit 09c2f95a ("scsi: mpt3sas: Swap I/O memory read value back
    to cpu endianness"), 64bit writes in _base_writeq() were rewritten to use
    __raw_writeq() instad of writeq().
    
    This introduced a bug apparent on powerpc64 systems such as the Raptor
    Talos II that causes the HBA to drop from the PCIe bus under heavy load and
    being reinitialized after a couple of seconds.
    
    It can easily be triggered on affacted systems by using something like
    
      fio --name=random-write --iodepth=4 --rw=randwrite --bs=4k --direct=0 \
        --size=128M --numjobs=64 --end_fsync=1
      fio --name=random-write --iodepth=4 --rw=randwrite --bs=64k --direct=0 \
        --size=128M --numjobs=64 --end_fsync=1
    
    a couple of times. In my case I tested it on both a ZFS raidz2 and a btrfs
    raid6 using LSI 9300-8i and 9400-8i controllers.
    
    The fix consists in resembling the write ordering of writeq() by adding a
    mandatory write memory barrier before device access and a compiler barrier
    afterwards. The additional MMIO barrier is superfluous.
    Signed-off-by: default avatarStephan Günther <moepi@moepi.net>
    Reported-by: default avatarMatt Corallo <linux@bluematt.me>
    Acked-by: default avatarSreekanth Reddy <Sreekanth.Reddy@broadcom.com>
    Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
    23c3828a
mpt3sas_base.c 194 KB