• Cyrill Gorcunov's avatar
    perf, x86: P4 PMU -- redesign cache events · 39ef13a4
    Cyrill Gorcunov authored
    To support cache events we have reserved the low 6 bits in
    hw_perf_event::config (which is a part of CCCR register
    configuration actually).
    
    These bits represent Replay Event mertic enumerated in
    enum P4_PEBS_METRIC. The caller should not care about
    which exact bits should be set and how -- the caller
    just chooses one P4_PEBS_METRIC entity and puts it into
    the config. The kernel will track it and set appropriate
    additional MSR registers (metrics) when needed.
    
    The reason for this redesign was the PEBS enable bit, which
    should not be set until DS (and PEBS sampling) support will
    be implemented properly.
    
    TODO
    ====
    
     - PEBS sampling (note it's tricky and works with _one_ counter only
       so for HT machines it will be not that easy to handle both threads)
    
     - tracking of PEBS registers state, a user might need to turn
       PEBS off completely (ie no PEBS enable, no UOP_tag) but some
       other event may need it, such events clashes and should not
       run simultaneously, at moment we just don't support such events
    
     - eventually export user space bits in separate header which will
       allow user apps to configure raw events more conveniently.
    Signed-off-by: default avatarCyrill Gorcunov <gorcunov@openvz.org>
    Signed-off-by: default avatarLin Ming <ming.m.lin@intel.com>
    Cc: Stephane Eranian <eranian@google.com>
    Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Cc: Frederic Weisbecker <fweisbec@gmail.com>
    LKML-Reference: <1278295769.9540.15.camel@minggr.sh.intel.com>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    39ef13a4
perf_event_p4.h 23.2 KB