• Mauro Carvalho Chehab's avatar
    i7core_edac: Add a memory check routine, based on device 3 function 4 · 442305b1
    Mauro Carvalho Chehab authored
    This function appears only on Xeon 5500 datasheet. Yet, testing with a
    Xeon 3503 showed that this is also implemented on other Nehalem
    processors.
    
    At the first read, MC_TEST_ERR_RCV1 and MC_TEST_ERR_RCV0 can contain any
    value. Modify CE error logic to update the error count only after the
    second read.
    
    An alternative approach would be to do a write at rcv0 and rcv1
    registers, but it seemed better to keep they untouched, since BIOS might
    eventually assume that they are exclusive for their usage.
    Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
    442305b1
i7core_edac.c 29.9 KB