• Daniel Vetter's avatar
    drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reporting · 7336df65
    Daniel Vetter authored
    Same treatment as for SERR_INT: If we clear only the bit for the pipe
    we're enabling (but unconditionally) then we can always check for
    possible underruns after having disabled the interrupt. That way pipe
    underruns won't be lost, but at worst only get reported in a delayed
    fashion.
    
    v2: The same logic bug as in the SERR handling change also existed
    here. The same bugfix of only reporting missed underruns when the
    error interrupt was masked applies, too.
    
    v3: Do the same fixes as for the SERR handling that Paulo suggested in
    his review:
    - s/%i/%c/ fix in the debug output
    - move the DE_ERR_INT_IVB read into the respective if block
    
    Cc: Paulo Zanoni <przanoni@gmail.com>
    Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    [danvet: Fix up the checkpatch bikeshed Paulo noticed.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    7336df65
i915_reg.h 187 KB