During receive processing, the tg3 card updates rx_producer (the
hardware position in the receive ring) and the opaque cookie. Due to PCI
rules the stores happen in order. However the cpu may reorder the reads.

In these sort of cases there is usually a data dependency between
reading the index and looking up the data (since we use the index to
load the data). I think all cpus except alpha guarantee the reads
happen in order in this case.

However in this particular case we load hw_idx, compare it to sw_idx and
then use sw_idx to locate the opaque cookie. There is no data dependency
in this case. We need a read memory barrier between the read of
rx_producer and the opaque cookie to enforce ordering.

Thanks to Olof Johansson, Michael Chan and Broadcom for their assistance
in finding this bug.
Signed-off-by: Anton Blanchard <anton@samba.org>