• Paulo Zanoni's avatar
    drm/i915: add SW tracking to FBC enabling · 9adccc60
    Paulo Zanoni authored
    Currently, calling intel_fbc_enabled() will trigger a register read.
    And we call it a lot of times, even when FBC is disabled, so saving a
    few cycles would be a good thing.
    
    Another reason for this patch is because we currently call
    intel_fbc_enabled() while the HW is runtime suspended, so the read
    makes no sense and triggers a WARN. This happens even if FBC is
    disabled by default. Of course one could argue that we just shouldn't
    be calling intel_fbc_enabled() while the driver is runtime suspended,
    and I agree that's a good argument, but I still think that the reason
    explained in the first paragraph already justifies the patch.
    This problem can easily be reproduced with many subtests of
    igt/pm_rpm, and it is a regression introduced by:
    
        commit c5ad011d
        Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
        Date:   Mon Aug 4 03:51:38 2014 -0700
            drm/i915: FBC flush nuke for BDW
    
    Testcase: igt/pm_rpm/cursor (and others)
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    9adccc60
i915_drv.h 89.8 KB