- When not low-power, only set GPIO enables in lclctrl on
5700 chips
- Follow all writes to foo DMAC_MODE with a readback and
udelay(40)
- Be explicit about the fact that the driver disables wake-on-lan
by default and how the user may enable it
- A few NIC_SRAM_DATA_CFG_foo bits were wrong or missing
- Clock control programming for some chips when going to low
power mode was wrong.
- Bump driver version/reldata for release
- PCI write posting fixes
  * Sanitize every PCI write that requires a delay afterwards by
    doing a dummy read back from the register.
  * Handle the interesting case of this when doing a core-clock
    reset by using PCI config space indirect writes to GRC_MISC_CFG
    since we cannot do an MMIO read back from the chip during this
    reset event because it clears MMIO space enable in PCI_CONFIG
  * Add a new tg3_flag TG3_FLAG_MBOX_WRITE_REORDER which is set
    on chipsets that may violate PCI write ordering rules, when
    set we always read back from tx/rx ring mailbox registers after
    a write to guarentee the writes appear to the chip in order.
- Make sure to always enable AS_MASTER bits when necessary
- PHY reset fixes
  * Always reset PHY on init, for every chip revision
  * Program 5703 specific PHY stuff after the reset
  * Always enable Ethernet@WireSpeed after that reset
  * Always set ADVERTISE_PAUSE_CAP in initial adv reg.