Finally, setup the VIU registers and start the AFBC decoder to support
displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs.

The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.

The vsync irq must still be left enabled otherwise the RDMA modules isn't
trigerred when the interrupt line is masked.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-10-narmstrong@baylibre.com