• Huacai Chen's avatar
    MIPS: Loongson-3: Fix CPU UART irq delivery problem · d06f8a2f
    Huacai Chen authored
    Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
    other CPUs) may cause interrupts be lost, especially in multi-package
    machines (Package-0's UART irq cannot be delivered to others). So make
    mask_loongson_irq() and unmask_loongson_irq() be no-ops.
    
    The original problem (UART IRQ may deliver to any core) is also because
    of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to
    remove all of the stuff.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Patchwork: https://patchwork.linux-mips.org/patch/20433/
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: James Hogan <jhogan@kernel.org>
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: Huacai Chen <chenhuacai@gmail.com>
    d06f8a2f
irq.c 3.87 KB