• Paul Walmsley's avatar
    [ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type · e4707dd3
    Paul Walmsley authored
    This patch adds a Non-cacheable Normal ARM executable memory type,
    MT_MEMORY_NONCACHED.
    
    On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
    the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
    VDD2 voltage domain, and its clock frequency must change along with
    voltage. The SDRC clock change code cannot run from SDRAM itself,
    since SDRAM accesses are paused during the clock change. So the
    current implementation of the DVFS code executes from OMAP on-chip
    SRAM, aka "OCM RAM."
    
    If the OCM RAM pages are marked as Cacheable, the ARM cache controller
    will attempt to flush dirty cache lines to the SDRC, so it can fill
    those lines with OCM RAM instruction code. The problem is that the
    SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
    subsystem to hang.
    
    TI's original solution to this problem was to mark the OCM RAM
    sections as Strongly Ordered memory, thus preventing caching. This is
    overkill: since the memory is marked as non-bufferable, OCM RAM writes
    become needlessly slow. The idea of "Strongly Ordered SRAM" is also
    conceptually disturbing. Previous LAKML list discussion is here:
    
    http://www.spinics.net/lists/arm-kernel/msg54312.html
    
    This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
    patch.
    
    Cc: Richard Woodruff <r-woodruff2@ti.com>
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    e4707dd3
mmu.c 25.9 KB