• Vineet Gupta's avatar
    ARCv2: intc: Allow interruption by lowest priority interrupt · dec2b284
    Vineet Gupta authored
    ARC HS Cores support configurable multiple interrupt priorities of upto
    16 levels.
    
    There is processor "interrupt preemption threshhold" in STATUS32.E[4:1]
    And several places need to set this up:
    1. seed value as kernel is booting
    2. seed value for user space programs
    3. Arg to SLEEP instruction in idle task (what interrupt prio can wake)
    4. Per-IRQ line prioirty (i.e. what is the priority of interrupt
       raised by a peripheral or timer or perf counter...
    
    Currently above sites use the highest priority 0. This can be potential
    problem when multiple priorities are supported. e.g. user space could
    only be interrupted by P0 interrupt, not others...
    So turn this over and instead make default interruption level to be
    the lowest priority possible 15. This should be fine even if there are
    fewer priority levels configured (say two: P0 HIGH, P1 LOW)
    
    This feature also effectively disables FIRQ feature if present in
    hardware config. With old code, a P0 interrupt would be FIRQ, needing
    special handling (ISR or Register Banks) which is NOT supported yet.
    Now it not be P0 (P15 or whatever is lowest prio) so FIRQ is not
    triggered.
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    dec2b284
intc-arcv2.c 4.18 KB