Commit 13409d27 authored by Michael Walle's avatar Michael Walle Committed by Mark Brown

ASoC: wm8904: configure sysclk/FLL automatically

This adds a new mode WM8904_CLK_AUTO which automatically enables the FLL
if a frequency different than the MCLK is set.

These additions make the codec work with the simple-card driver in
general and especially in systems where the MCLK doesn't match the
required clock.
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Acked-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20191108203152.19098-1-michael@walle.ccSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent e2db787b
...@@ -1410,34 +1410,6 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream, ...@@ -1410,34 +1410,6 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream,
return 0; return 0;
} }
static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8904_CLK_MCLK:
priv->sysclk_src = clk_id;
priv->mclk_rate = freq;
break;
case WM8904_CLK_FLL:
priv->sysclk_src = clk_id;
break;
default:
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
wm8904_configure_clocking(component);
return 0;
}
static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{ {
struct snd_soc_component *component = dai->component; struct snd_soc_component *component = dai->component;
...@@ -1824,6 +1796,50 @@ static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, ...@@ -1824,6 +1796,50 @@ static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
return 0; return 0;
} }
static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
unsigned long mclk_freq;
int ret;
switch (clk_id) {
case WM8904_CLK_AUTO:
mclk_freq = clk_get_rate(priv->mclk);
/* enable FLL if a different sysclk is desired */
if (mclk_freq != freq) {
priv->sysclk_src = WM8904_CLK_FLL;
ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
WM8904_FLL_MCLK,
mclk_freq, freq);
if (ret)
return ret;
break;
}
clk_id = WM8904_CLK_MCLK;
/* fallthrough */
case WM8904_CLK_MCLK:
priv->sysclk_src = clk_id;
priv->mclk_rate = freq;
break;
case WM8904_CLK_FLL:
priv->sysclk_src = clk_id;
break;
default:
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
wm8904_configure_clocking(component);
return 0;
}
static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
{ {
struct snd_soc_component *component = codec_dai->component; struct snd_soc_component *component = codec_dai->component;
......
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#ifndef _WM8904_H #ifndef _WM8904_H
#define _WM8904_H #define _WM8904_H
#define WM8904_CLK_AUTO 0
#define WM8904_CLK_MCLK 1 #define WM8904_CLK_MCLK 1
#define WM8904_CLK_FLL 2 #define WM8904_CLK_FLL 2
......
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