Commit 16270a92 authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Lorenzo Pieralisi

PCI: designware-ep: Fix the Header Type check

The current check will result in the multiple function device
fails to initialize. So fix the check by masking out the
multiple function bit.

Link: https://lore.kernel.org/r/20200818092746.24366-1-Zhiqiang.Hou@nxp.com
Fixes: 0b24134f ("PCI: dwc: Add validation that PCIe core is set to correct mode")
Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 9123e3a7
...@@ -505,7 +505,8 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) ...@@ -505,7 +505,8 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
u32 reg; u32 reg;
int i; int i;
hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) &
PCI_HEADER_TYPE_MASK;
if (hdr_type != PCI_HEADER_TYPE_NORMAL) { if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
dev_err(pci->dev, dev_err(pci->dev,
"PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
......
...@@ -76,6 +76,7 @@ ...@@ -76,6 +76,7 @@
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */ #define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_MASK 0x7f
#define PCI_HEADER_TYPE_NORMAL 0 #define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1 #define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2 #define PCI_HEADER_TYPE_CARDBUS 2
......
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