Commit 1affdc35 authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include',...

Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next

  - Tag various drivers with SPDX license tags
  - Support dynamic frequency switching (DFS) on qcom SDM845 GCC
  - Only use s2mps11 dt-binding defines instead of redefining them in the driver
  - Add some more missing clks to qcom MSM8996 GCC
  - Quad SPI clks on qcom SDM845

* clk-spdx:
  clk: mvebu: use SPDX-License-Identifier
  clk: renesas: Convert to SPDX identifiers
  clk: renesas: use SPDX identifier for Renesas drivers
  clk: s2mps11,s3c64xx: Add SPDX license identifiers
  clk: max77686: Add SPDX license identifiers

* clk-qcom-dfs:
  clk: qcom: Allocate space for NULL terimation in DFS table
  clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
  clk: qcom: Add support for RCG to register for DFS

* clk-smp2s11-include:
  clk: s2mps11: Use existing defines from bindings for clock IDs

* clk-qcom-8996-missing:
  clk: qcom: Add some missing gcc clks for msm8996

* clk-qcom-qspi:
  clk: qcom: Add qspi (Quad SPI) clocks for sdm845
  clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
...@@ -17,12 +17,7 @@ ...@@ -17,12 +17,7 @@
#include <linux/mfd/samsung/s5m8767.h> #include <linux/mfd/samsung/s5m8767.h>
#include <linux/mfd/samsung/core.h> #include <linux/mfd/samsung/core.h>
enum { #include <dt-bindings/clock/samsung,s2mps11.h>
S2MPS11_CLK_AP = 0,
S2MPS11_CLK_CP,
S2MPS11_CLK_BT,
S2MPS11_CLKS_NUM,
};
struct s2mps11_clk { struct s2mps11_clk {
struct sec_pmic_dev *iodev; struct sec_pmic_dev *iodev;
......
...@@ -163,4 +163,15 @@ extern const struct clk_ops clk_pixel_ops; ...@@ -163,4 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops; extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops; extern const struct clk_ops clk_rcg2_shared_ops;
struct clk_rcg_dfs_data {
struct clk_rcg2 *rcg;
struct clk_init_data *init;
};
#define DEFINE_RCG_DFS(r) \
{ .rcg = &r##_src, .init = &r##_init }
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
const struct clk_rcg_dfs_data *rcgs,
size_t len);
#endif #endif
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/math64.h> #include <linux/math64.h>
#include <linux/slab.h>
#include <asm/div64.h> #include <asm/div64.h>
...@@ -40,6 +41,14 @@ ...@@ -40,6 +41,14 @@
#define N_REG 0xc #define N_REG 0xc
#define D_REG 0x10 #define D_REG 0x10
/* Dynamic Frequency Scaling */
#define MAX_PERF_LEVEL 8
#define SE_CMD_DFSR_OFFSET 0x14
#define SE_CMD_DFS_EN BIT(0)
#define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
#define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
#define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
enum freq_policy { enum freq_policy {
FLOOR, FLOOR,
CEIL, CEIL,
...@@ -929,3 +938,189 @@ const struct clk_ops clk_rcg2_shared_ops = { ...@@ -929,3 +938,189 @@ const struct clk_ops clk_rcg2_shared_ops = {
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
}; };
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
/* Common APIs to be used for DFS based RCGR */
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
struct freq_tbl *f)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *p;
unsigned long prate = 0;
u32 val, mask, cfg, mode;
int i, num_parents;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
mask = BIT(rcg->hid_width) - 1;
f->pre_div = 1;
if (cfg & mask)
f->pre_div = cfg & mask;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++) {
if (cfg == rcg->parent_map[i].cfg) {
f->src = rcg->parent_map[i].src;
p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
prate = clk_hw_get_rate(p);
}
}
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
if (mode) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
&val);
val &= mask;
f->m = val;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
&val);
val = ~val;
val &= mask;
val += f->m;
f->n = val;
}
f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
}
static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
{
struct freq_tbl *freq_tbl;
int i;
/* Allocate space for 1 extra since table is NULL terminated */
freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
if (!freq_tbl)
return -ENOMEM;
rcg->freq_tbl = freq_tbl;
for (i = 0; i < MAX_PERF_LEVEL; i++)
clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
return 0;
}
static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
if (!rcg->freq_tbl) {
ret = clk_rcg2_dfs_populate_freq_table(rcg);
if (ret) {
pr_err("Failed to update DFS tables for %s\n",
clk_hw_get_name(hw));
return ret;
}
}
return clk_rcg2_determine_rate(hw, req);
}
static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
level &= GENMASK(4, 1);
level >>= 1;
if (rcg->freq_tbl)
return rcg->freq_tbl[level].freq;
/*
* Assume that parent_rate is actually the parent because
* we can't do any better at figuring it out when the table
* hasn't been populated yet. We only populate the table
* in determine_rate because we can't guarantee the parents
* will be registered with the framework until then.
*/
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
&cfg);
mask = BIT(rcg->hid_width) - 1;
pre_div = 1;
if (cfg & mask)
pre_div = cfg & mask;
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
if (mode) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
m &= mask;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
n = ~n;
n &= mask;
n += m;
}
return calc_rate(parent_rate, m, n, mode, pre_div);
}
static const struct clk_ops clk_rcg2_dfs_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.determine_rate = clk_rcg2_dfs_determine_rate,
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
struct regmap *regmap)
{
struct clk_rcg2 *rcg = data->rcg;
struct clk_init_data *init = data->init;
u32 val;
int ret;
ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
if (ret)
return -EINVAL;
if (!(val & SE_CMD_DFS_EN))
return 0;
/*
* Rate changes with consumer writing a register in
* their own I/O region
*/
init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = &clk_rcg2_dfs_ops;
rcg->freq_tbl = NULL;
pr_debug("DFS registered for clk %s\n", init->name);
return 0;
}
int qcom_cc_register_rcg_dfs(struct regmap *regmap,
const struct clk_rcg_dfs_data *rcgs, size_t len)
{
int i, ret;
for (i = 0; i < len; i++) {
ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
if (ret) {
const char *name = rcgs[i].init->name;
pr_err("DFS register failed for clk %s\n", name);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
...@@ -260,6 +260,36 @@ static struct clk_alpha_pll_postdiv gpll0 = { ...@@ -260,6 +260,36 @@ static struct clk_alpha_pll_postdiv gpll0 = {
}, },
}; };
static struct clk_branch gcc_mmss_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_div_clk",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_gpll0_div_clk",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops
},
},
};
static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000, .offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
...@@ -2951,6 +2981,20 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { ...@@ -2951,6 +2981,20 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
}, },
}; };
static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
.halt_reg = 0x82014,
.clkr = {
.enable_reg = 0x82014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_pnoc_ahb_clk",
.parent_names = (const char *[]){ "periph_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_ufs_axi_clk = { static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x83014, .halt_reg = 0x83014,
.clkr = { .clkr = {
...@@ -2981,6 +3025,34 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { ...@@ -2981,6 +3025,34 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
}, },
}; };
static struct clk_branch gcc_dcc_ahb_clk = {
.halt_reg = 0x84004,
.clkr = {
.enable_reg = 0x84004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_ahb_clk",
.parent_names = (const char *[]){ "config_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
.halt_reg = 0x85000,
.clkr = {
.enable_reg = 0x85000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
.parent_names = (const char *[]){ "config_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_ahb_clk = { static struct clk_branch gcc_qspi_ahb_clk = {
.halt_reg = 0x8b004, .halt_reg = 0x8b004,
.clkr = { .clkr = {
...@@ -3039,6 +3111,20 @@ static struct clk_branch gcc_hdmi_clkref_clk = { ...@@ -3039,6 +3111,20 @@ static struct clk_branch gcc_hdmi_clkref_clk = {
}, },
}; };
static struct clk_branch gcc_edp_clkref_clk = {
.halt_reg = 0x88004,
.clkr = {
.enable_reg = 0x88004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_edp_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_clkref_clk = { static struct clk_branch gcc_ufs_clkref_clk = {
.halt_reg = 0x88008, .halt_reg = 0x88008,
.clkr = { .clkr = {
...@@ -3095,6 +3181,62 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { ...@@ -3095,6 +3181,62 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
}, },
}; };
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_names = (const char *[]){ "config_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
.halt_reg = 0x8a004,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mnoc_bimc_axi_clk",
.parent_names = (const char *[]){ "system_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a024,
.clkr = {
.enable_reg = 0x8a024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.parent_names = (const char *[]){ "system_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x8a028,
.clkr = {
.enable_reg = 0x8a028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_names = (const char *[]){ "system_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *gcc_msm8996_hws[] = { static struct clk_hw *gcc_msm8996_hws[] = {
&xo.hw, &xo.hw,
&gpll0_early_div.hw, &gpll0_early_div.hw,
...@@ -3355,6 +3497,7 @@ static struct clk_regmap *gcc_msm8996_clocks[] = { ...@@ -3355,6 +3497,7 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr, [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr, [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr, [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
...@@ -3365,6 +3508,15 @@ static struct clk_regmap *gcc_msm8996_clocks[] = { ...@@ -3365,6 +3508,15 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr, [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
}; };
static struct gdsc *gcc_msm8996_gdscs[] = { static struct gdsc *gcc_msm8996_gdscs[] = {
......
...@@ -356,6 +356,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { ...@@ -356,6 +356,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
}, },
}; };
static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0), F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0),
...@@ -396,18 +418,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { ...@@ -396,18 +418,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
{ } { }
}; };
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17034, .cmd_rcgr = 0x17034,
.mnd_width = 16, .mnd_width = 16,
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
.name = "gcc_qupv3_wrap0_s0_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s1_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
...@@ -416,12 +447,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ...@@ -416,12 +447,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
.name = "gcc_qupv3_wrap0_s1_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s2_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
...@@ -430,12 +463,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ...@@ -430,12 +463,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
.name = "gcc_qupv3_wrap0_s2_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s3_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
...@@ -444,12 +479,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ...@@ -444,12 +479,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
.name = "gcc_qupv3_wrap0_s3_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s4_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
...@@ -458,12 +495,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ...@@ -458,12 +495,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
.name = "gcc_qupv3_wrap0_s4_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s5_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
...@@ -472,12 +511,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ...@@ -472,12 +511,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
.name = "gcc_qupv3_wrap0_s5_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s6_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
...@@ -486,12 +527,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ...@@ -486,12 +527,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
.name = "gcc_qupv3_wrap0_s6_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap0_s7_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
...@@ -500,12 +543,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ...@@ -500,12 +543,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
.name = "gcc_qupv3_wrap0_s7_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s0_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
...@@ -514,12 +559,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ...@@ -514,12 +559,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
.name = "gcc_qupv3_wrap1_s0_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s1_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
...@@ -528,12 +575,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ...@@ -528,12 +575,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
.name = "gcc_qupv3_wrap1_s1_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s2_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
...@@ -542,12 +591,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ...@@ -542,12 +591,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
.name = "gcc_qupv3_wrap1_s2_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s3_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
...@@ -556,12 +607,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ...@@ -556,12 +607,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
.name = "gcc_qupv3_wrap1_s3_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s4_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
...@@ -570,12 +623,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ...@@ -570,12 +623,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
.name = "gcc_qupv3_wrap1_s4_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s5_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
...@@ -584,12 +639,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ...@@ -584,12 +639,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
.name = "gcc_qupv3_wrap1_s5_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s6_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
...@@ -598,12 +655,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { ...@@ -598,12 +655,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
.name = "gcc_qupv3_wrap1_s6_clk_src", };
.parent_names = gcc_parent_names_0,
.num_parents = 4, static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
.ops = &clk_rcg2_shared_ops, .name = "gcc_qupv3_wrap1_s7_clk_src",
}, .parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
}; };
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
...@@ -612,12 +671,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { ...@@ -612,12 +671,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.hid_width = 5, .hid_width = 5,
.parent_map = gcc_parent_map_0, .parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
.ops = &clk_rcg2_shared_ops,
},
}; };
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
...@@ -1933,6 +1987,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = { ...@@ -1933,6 +1987,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = {
}, },
}; };
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_names = (const char *[]){
"gcc_qspi_core_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = { static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17030, .halt_reg = 0x17030,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_VOTED,
...@@ -3381,6 +3466,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { ...@@ -3381,6 +3466,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
[GPLL4] = &gpll4.clkr, [GPLL4] = &gpll4.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
}; };
static const struct qcom_reset_map gcc_sdm845_resets[] = { static const struct qcom_reset_map gcc_sdm845_resets[] = {
...@@ -3458,9 +3546,29 @@ static const struct of_device_id gcc_sdm845_match_table[] = { ...@@ -3458,9 +3546,29 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
}; };
MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
};
static int gcc_sdm845_probe(struct platform_device *pdev) static int gcc_sdm845_probe(struct platform_device *pdev)
{ {
struct regmap *regmap; struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
if (IS_ERR(regmap)) if (IS_ERR(regmap))
...@@ -3470,6 +3578,11 @@ static int gcc_sdm845_probe(struct platform_device *pdev) ...@@ -3470,6 +3578,11 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
} }
......
...@@ -235,6 +235,15 @@ ...@@ -235,6 +235,15 @@
#define GCC_RX1_USB2_CLKREF_CLK 218 #define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_EDP_CLKREF_CLK 221
#define GCC_MSS_CFG_AHB_CLK 222
#define GCC_MSS_Q6_BIMC_AXI_CLK 223
#define GCC_MSS_SNOC_AXI_CLK 224
#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
#define GCC_DCC_AHB_CLK 226
#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
#define GCC_MMSS_GPLL0_DIV_CLK 228
#define GCC_MSS_GPLL0_DIV_CLK 229
#define GCC_SYSTEM_NOC_BCR 0 #define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1 #define GCC_CONFIG_NOC_BCR 1
......
...@@ -194,6 +194,9 @@ ...@@ -194,6 +194,9 @@
#define GPLL4 184 #define GPLL4 184
#define GCC_CPUSS_DVM_BUS_CLK 185 #define GCC_CPUSS_DVM_BUS_CLK 185
#define GCC_CPUSS_GNOC_CLK 186 #define GCC_CPUSS_GNOC_CLK 186
#define GCC_QSPI_CORE_CLK_SRC 187
#define GCC_QSPI_CORE_CLK 188
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
/* GCC Resets */ /* GCC Resets */
#define GCC_MMSS_BCR 0 #define GCC_MMSS_BCR 0
......
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