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Commit 2ec3240f authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "We continue ramping up platform support for 64-bit ARM machines, with
  111 individual non-merge changesets touching 21 platforms.

  The LG1312 platform is completely new and is the first ARM platform by
  LG that we support in the mainline kernel.  Two other SoCs got added
  that are updated versions of existing SoC families, so the port mainly
  consists of new dts files:

   - The Hisilicon Hip06/D03 is the latest server platform from
     Huawei/Hisilicon, and follows the Hip05/D02 platform.

   - Rockchip RK3399 follows the 32-bit RK3288 that is popular in
     low-end Chromebooks and the 64-bit RK3368 that is mainly found in
     chinese Android TV boxes.

  The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620) gets a
  long-awaited overhaul with a lot of devices enabled in the DT, so it
  should be much more usable with a mainline kernel now.  See also

     https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd

  A lot of work went into enabling new device drivers on existing
  machines, but we also have a couple of new commercially available
  machines:

   - Google Pixel C laptop based on Tegra210
   - Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905)
   - Geekbuying GeekBox based on Rockchip RK3368

  And finally, a couple of reference or development platforms that are
  not end-user platforms but are used for trying out the respective SoC
  platforms:

   - Amlogic Meson GXBB P200 and P201 development systems
   - NXP Layerscape 1043A QDS development board
   - Hisilicon Hip06 D03 server board, as mentioned above
   - LG1312 Reference Design
   - RK3399 Evaluation Board"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
  arm64: dts: marvell: add XOR node for Armada 3700 SoC
  dt-bindings: document rockchip rk3399-evb board
  arm64: dts: rockchip: add dts file for RK3399 evaluation board
  arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
  dt-bindings: rockchip-dw-mshc: add description for rk3399
  arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
  arm64: dts: marvell: Rename armada-37xx USB node
  arm64: dts: marvell: Clean up armada-3720-db
  Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
  arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
  arm64: dts: hip05: Add nor flash support
  arm64: dts: hip05: fix its node without msi-cells
  arm64: dts: r8a7795: Don't disable referenced optional clocks
  arm64: dts: salvator-x: populate EXTALR
  arm64: dts: r8a7795: enable PCIe on Salvator-X
  arm64: dts: r8a7795: Add PCIe nodes
  arm64: tegra: Add IOMMU node to GM20B on Tegra210
  arm64: tegra: Add reference clock to GM20B on Tegra210
  dt-bindings: Add documentation for GM20B GPU
  dt-bindings: gk20a: Document iommus property
  ...
parents f7df9be0 9910f5b1
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Documentation/devicetree/bindings/arm/amlogic.txt
View file @ 2ec3240f
......@@ -25,3 +25,6 @@ Board compatible values:
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
Documentation/devicetree/bindings/arm/fsl.txt
View file @ 2ec3240f
......@@ -135,6 +135,10 @@ LS1043A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
LS1043A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
......
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View file @ 2ec3240f
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
HiP04 D01 Board
Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hip04-d01";
- compatible = "hisilicon,hi6220";
HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
HiKey Board
HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
- compatible = "hisilicon,hip04-d01";
HiP05 D02 Board
Required root node properties:
- compatible = "hisilicon,hip05-d02";
HiP06 D03 Board
Required root node properties:
- compatible = "hisilicon,hip06-d03";
Hisilicon system controller
Required properties:
......
Documentation/devicetree/bindings/arm/rockchip.txt
View file @ 2ec3240f
......@@ -39,6 +39,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288";
- GeekBuying GeekBox:
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
......@@ -101,4 +105,8 @@ Rockchip platforms device tree bindings
- Rockchip RK3228 Evaluation board:
Required root node properties:
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt 0 → 100644
View file @ 2ec3240f
NVIDIA Tegra186 GPIO controllers
Tegra186 contains two GPIO controllers; a main controller and an "AON"
controller. This binding document applies to both controllers. The register
layouts for the controllers share many similarities, but also some significant
differences. Hence, this document describes closely related but different
bindings and compatible values.
The Tegra186 GPIO controller allows software to set the IO direction of, and
read/write the value of, numerous GPIO signals. Routing of GPIO signals to
package balls is under the control of a separate pin controller HW block. Two
major sets of registers exist:
a) Security registers, which allow configuration of allowed access to the GPIO
register set. These registers exist in a single contiguous block of physical
address space. The size of this block, and the security features available,
varies between the different GPIO controllers.
Access to this set of registers is not necessary in all circumstances. Code
that wishes to configure access to the GPIO registers needs access to these
registers to do so. Code which simply wishes to read or write GPIO data does not
need access to these registers.
b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
controllers, these registers are exposed via multiple "physical aliases" in
address space, each of which access the same underlying state. See the hardware
documentation for rationale. Any particular GPIO client is expected to access
just one of these physical aliases.
Tegra HW documentation describes a unified naming convention for all GPIOs
implemented by the SoC. Each GPIO is assigned to a port, and a port may control
a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
or GPIO_PCC3.
The number of ports implemented by each GPIO controller varies. The number of
implemented GPIOs within each port varies. GPIO registers within a controller
are grouped and laid out according to the port they affect.
The mapping from port name to the GPIO controller that implements that port, and
the mapping from port name to register offset within a controller, are both
extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
describes the port-level mapping. In that file, the naming convention for ports
matches the HW documentation. The values chosen for the names are alphabetically
sorted within a particular controller. Drivers need to map between the DT GPIO
IDs and HW register offsets using a lookup table.
Each GPIO controller can generate a number of interrupt signals. Each signal
represents the aggregate status for all GPIOs within a set of ports. Thus, the
number of interrupt signals generated by a controller varies as a rough function
of the number of ports it implements. Note that the HW documentation refers to
both the overall controller HW module and the sets-of-ports as "controllers".
Each GPIO controller in fact generates multiple interrupts signals for each set
of ports. Each GPIO may be configured to feed into a specific one of the
interrupt signals generated by a set-of-ports. The intent is for each generated
signal to be routed to a different CPU, thus allowing different CPUs to each
handle subsets of the interrupts within a port. The status of each of these
per-port-set signals is reported via a separate register. Thus, a driver needs
to know which status register to observe. This binding currently defines no
configuration mechanism for this. By default, drivers should use register
GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
define a property to configure this.
Required properties:
- compatible
Array of strings.
One of:
- "nvidia,tegra186-gpio".
- "nvidia,tegra186-gpio-aon".
- reg-names
Array of strings.
Contains a list of names for the register spaces described by the reg
property. May contain the following entries, in any order:
- "gpio": Mandatory. GPIO control registers. This may cover either:
a) The single physical alias that this OS should use.
b) All physical aliases that exist in the controller. This is
appropriate when the OS is responsible for managing assignment of
the physical aliases.
- "security": Optional. Security configuration registers.
Users of this binding MUST look up entries in the reg property by name,
using this reg-names property to do so.
- reg
Array of (physical base address, length) tuples.
Must contain one entry per entry in the reg-names property, in a matching
order.
- interrupts
Array of interrupt specifiers.
The interrupt outputs from the HW block, one per set of ports, in the
order the HW manual describes them. The number of entries required varies
depending on compatible value:
- "nvidia,tegra186-gpio": 6 entries.
- "nvidia,tegra186-gpio-aon": 1 entry.
- gpio-controller
Boolean.
Marks the device node as a GPIO controller/provider.
- #gpio-cells
Single-cell integer.
Must be <2>.
Indicates how many cells are used in a consumer's GPIO specifier.
In the specifier:
- The first cell is the pin number.
See <dt-bindings/gpio/tegra186-gpio.h>.
- The second cell contains flags:
- Bit 0 specifies polarity
- 0: Active-high (normal).
- 1: Active-low (inverted).
- interrupt-controller
Boolean.
Marks the device node as an interrupt controller/provider.
- #interrupt-cells
Single-cell integer.
Must be <2>.
Indicates how many cells are used in a consumer's interrupt specifier.
In the specifier:
- The first cell is the GPIO number.
See <dt-bindings/gpio/tegra186-gpio.h>.
- The second cell is contains flags:
- Bits [3:0] indicate trigger type and level:
- 1: Low-to-high edge triggered.
- 2: High-to-low edge triggered.
- 4: Active high level-sensitive.
- 8: Active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
Example:
#include <dt-bindings/interrupt-controller/irq.h>
gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";
reg =
<0x0 0x2200000 0x0 0x10000>,
<0x0 0x2210000 0x0 0x10000>;
interrupts =
<0 47 IRQ_TYPE_LEVEL_HIGH>,
<0 50 IRQ_TYPE_LEVEL_HIGH>,
<0 53 IRQ_TYPE_LEVEL_HIGH>,
<0 56 IRQ_TYPE_LEVEL_HIGH>,
<0 59 IRQ_TYPE_LEVEL_HIGH>,
<0 180 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@c2f0000 {
compatible = "nvidia,tegra186-gpio-aon";
reg-names = "security", "gpio";
reg =
<0x0 0xc2f0000 0x0 0x1000>,
<0x0 0xc2f1000 0x0 0x1000>;
interrupts =
<0 60 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
View file @ 2ec3240f
NVIDIA GK20A Graphics Processing Unit
NVIDIA Tegra Graphics Processing Units
Required properties:
- compatible: "nvidia,<chip>-<gpu>"
- compatible: "nvidia,<gpu>"
Currently recognized values:
- nvidia,tegra124-gk20a
- nvidia,gk20a
- nvidia,gm20b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
......@@ -19,14 +20,20 @@ Required properties:
- clock-names: Must include the following entries:
- gpu
- pwr
If the compatible string is "nvidia,gm20b", then the following clock
is also required:
- ref
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- gpu
Example:
Optional properties:
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
gpu@0,57000000 {
Example for GK20A:
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
......@@ -39,5 +46,25 @@ Example:
clock-names = "gpu", "pwr";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
Example for GM20B:
gpu@57000000 {
compatible = "nvidia,gm20b";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&tegra_car TEGRA210_CLK_GPU>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
clock-names = "gpu", "pwr", "ref";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
View file @ 2ec3240f
......@@ -30,11 +30,90 @@ Required properties:
region may not be present in some scenarios, such
as in the device tree presented to a virtual machine.
- msi-parent
Value type: <phandle>
Definition: Must be present and point to the MSI controller node
handling message interrupts for the MC.
- ranges
Value type: <prop-encoded-array>
Definition: A standard property. Defines the mapping between the child
MC address space and the parent system address space.
The MC address space is defined by 3 components:
<region type> <offset hi> <offset lo>
Valid values for region type are
0x0 - MC portals
0x1 - QBMAN portals
- #address-cells
Value type: <u32>
Definition: Must be 3. (see definition in 'ranges' property)
- #size-cells
Value type: <u32>
Definition: Must be 1.
Sub-nodes:
The fsl-mc node may optionally have dpmac sub-nodes that describe
the relationship between the Ethernet MACs which belong to the MC
and the Ethernet PHYs on the system board.
The dpmac nodes must be under a node named "dpmacs" which contains
the following properties:
- #address-cells
Value type: <u32>
Definition: Must be present if dpmac sub-nodes are defined and must
have a value of 1.
- #size-cells
Value type: <u32>
Definition: Must be present if dpmac sub-nodes are defined and must
have a value of 0.
These nodes must have the following properties:
- compatible
Value type: <string>
Definition: Must be "fsl,qoriq-mc-dpmac".
- reg
Value type: <prop-encoded-array>
Definition: Specifies the id of the dpmac.
- phy-handle
Value type: <phandle>
Definition: Specifies the phandle to the PHY device node associated
with the this dpmac.
Example:
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
phy-handle = <&mdio0_phy0>;
}
}
};
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
View file @ 2ec3240f
......@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
Optional Properties:
* clocks: from common clock binding: if ciu_drive and ciu_sample are
......
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
View file @ 2ec3240f
......@@ -5,7 +5,8 @@ Required properties:
"fsl,imx7d-qspi", "fsl,imx6ul-qspi",
"fsl,ls1021a-qspi"
or
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
......
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
View file @ 2ec3240f
ARM Freescale DSPI controller
Required properties:
- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
"fsl,ls2085a-dspi"
or
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- clocks: from common clock binding: handle to dspi clock.
......
Documentation/devicetree/bindings/usb/usb-xhci.txt
View file @ 2ec3240f
......@@ -4,6 +4,7 @@ Required properties:
- compatible: should be one or more of
- "generic-xhci" for generic XHCI device
- "marvell,armada3700-xhci" for Armada 37xx SoCs
- "marvell,armada-375-xhci" for Armada 375 SoCs
- "marvell,armada-380-xhci" for Armada 38x SoCs
- "renesas,xhci-r8a7790" for r8a7790 SoC
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 2ec3240f
......@@ -93,6 +93,7 @@ firefly Firefly
focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
ge General Electric Company
geekbuying GeekBuying
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
......
arch/arm64/boot/dts/Makefile
View file @ 2ec3240f
......@@ -18,6 +18,7 @@ dts-dirs += rockchip
dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
dts-dirs += lg
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/amlogic/Makefile
View file @ 2ec3240f
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
......
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb.dtsi"
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&uart_AO {
status = "okay";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p200", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P200 Development Board";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p201", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P201 Development Board";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxbb.dtsi"
/ {
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
View file @ 2ec3240f
......@@ -48,7 +48,7 @@ / {
compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Meta";
memory {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
......
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
View file @ 2ec3240f
......@@ -48,7 +48,7 @@ / {
compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Pro";
memory {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
......
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
View file @ 2ec3240f
......@@ -48,7 +48,7 @@ / {
compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Telos";
memory {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
......
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View file @ 2ec3240f
......@@ -45,6 +45,10 @@
/ {
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
......
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View file @ 2ec3240f
......@@ -50,11 +50,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
......
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View file @ 2ec3240f
......@@ -543,7 +543,7 @@ pcie1: pcie@1f2c0000 {
};
sata1: sata@1a000000 {
compatible = "apm,xgene-ahci";
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a000000 0x0 0x1000>,
<0x0 0x1f200000 0x0 0x1000>,
<0x0 0x1f20d000 0x0 0x1000>,
......@@ -553,7 +553,7 @@ sata1: sata@1a000000 {
};
sata2: sata@1a200000 {
compatible = "apm,xgene-ahci";
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a200000 0x0 0x1000>,
<0x0 0x1f210000 0x0 0x1000>,
<0x0 0x1f21d000 0x0 0x1000>,
......@@ -563,7 +563,7 @@ sata2: sata@1a200000 {
};
sata3: sata@1a400000 {
compatible = "apm,xgene-ahci";
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a400000 0x0 0x1000>,
<0x0 0x1f220000 0x0 0x1000>,
<0x0 0x1f22d000 0x0 0x1000>,
......
arch/arm64/boot/dts/arm/juno-base.dtsi
View file @ 2ec3240f
......@@ -272,3 +272,13 @@ smb@08000000 {
/include/ "juno-motherboard.dtsi"
};
site2: tlx@60000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x60000000 0x10000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0>;
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
};
arch/arm64/boot/dts/broadcom/ns2-clock.dtsi 0 → 100644
View file @ 2ec3240f
/*
* BSD LICENSE
*
* Copyright (c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-ns2.h>
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
lcpll_ddr: lcpll_ddr@6501d058 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ddr";
reg = <0x6501d058 0x20>,
<0x6501c020 0x4>,
<0x6501d04c 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
"ddr", "ddr_ch2_unused",
"ddr_ch3_unused", "ddr_ch4_unused",
"ddr_ch5_unused";
};
lcpll_ports: lcpll_ports@6501d078 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ports";
reg = <0x6501d078 0x20>,
<0x6501c020 0x4>,
<0x6501d054 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ports", "wan", "rgmii",
"ports_ch2_unused",
"ports_ch3_unused",
"ports_ch4_unused",
"ports_ch5_unused";
};
genpll_scr: genpll_scr@6501d098 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-scr";
reg = <0x6501d098 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_scr", "scr", "fs",
"audio_ref", "scr_ch3_unused",
"scr_ch4_unused", "scr_ch5_unused";
};
iprocmed: iprocmed {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
iprocslow: iprocslow {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
genpll_sw: genpll_sw@6501d0c4 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-sw";
reg = <0x6501d0c4 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_sw", "rpe", "250", "nic",
"chimp", "port", "sdio";
};
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View file @ 2ec3240f
......@@ -72,6 +72,51 @@ &uart3 {
status = "ok";
};
&ssp0 {
status = "ok";
slic@0 {
compatible = "silabs,si3226x";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha = <1>;
spi-cpol = <1>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};
&ssp1 {
status = "ok";
at25@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
spi-cpha = <1>;
spi-cpol = <1>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};
&sdio0 {
status = "ok";
};
......
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file @ 2ec3240f
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
* Copyright (c) 2015 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
......@@ -33,8 +33,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>
/memreserve/ 0x84b00000 0x00000008;
/ {
compatible = "brcm,ns2";
interrupt-parent = <&gic>;
......@@ -49,8 +47,7 @@ A57_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
......@@ -58,8 +55,7 @@ A57_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
......@@ -67,8 +63,7 @@ A57_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 2>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
......@@ -76,8 +71,7 @@ A57_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 3>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
......@@ -86,6 +80,11 @@ CLUSTER0_L2: l2-cache@000 {
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
......@@ -110,33 +109,6 @@ pmu {
<&A57_3>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
iprocmed: iprocmed {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
iprocslow: iprocslow {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
};
pcie0: pcie@20020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x20020000 0 0x1000>;
......@@ -217,6 +189,27 @@ soc: soc {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
#include "ns2-clock.dtsi"
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&iprocslow>;
clock-names = "apb_pclk";
};
smmu: mmu@64000000 {
compatible = "arm,mmu-500";
reg = <0x64000000 0x40000>;
......@@ -258,68 +251,6 @@ smmu: mmu@64000000 {
mmu-masters;
};
lcpll_ddr: lcpll_ddr@6501d058 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ddr";
reg = <0x6501d058 0x20>,
<0x6501c020 0x4>,
<0x6501d04c 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
"ddr", "ddr_ch2_unused",
"ddr_ch3_unused", "ddr_ch4_unused",
"ddr_ch5_unused";
};
lcpll_ports: lcpll_ports@6501d078 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ports";
reg = <0x6501d078 0x20>,
<0x6501c020 0x4>,
<0x6501d054 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ports", "wan", "rgmii",
"ports_ch2_unused",
"ports_ch3_unused",
"ports_ch4_unused",
"ports_ch5_unused";
};
genpll_scr: genpll_scr@6501d098 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-scr";
reg = <0x6501d098 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_scr", "scr", "fs",
"audio_ref", "scr_ch3_unused",
"scr_ch4_unused", "scr_ch5_unused";
};
genpll_sw: genpll_sw@6501d0c4 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-sw";
reg = <0x6501d0c4 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_sw", "rpe", "250", "nic",
"chimp", "port", "sdio";
};
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
};
reboot@65024000 {
compatible ="syscon-reboot";
regmap = <&crmu>;
offset = <0x90>;
mask = <0xfffffffd>;
};
gic: interrupt-controller@65210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
......@@ -328,6 +259,8 @@ gic: interrupt-controller@65210000 {
<0x65220000 0x1000>,
<0x65240000 0x2000>,
<0x65260000 0x1000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_HIGH)>;
};
timer0: timer@66030000 {
......@@ -408,6 +341,28 @@ uart3: serial@66130000 {
status = "disabled";
};
ssp0: ssp@66180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66180000 0x1000>;
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "spiclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssp1: ssp@66190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66190000 0x1000>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "spiclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hwrng: hwrng@66220000 {
compatible = "brcm,iproc-rng200";
reg = <0x66220000 0x28>;
......
arch/arm64/boot/dts/exynos/exynos7-tmu-sensor-conf.dtsi 0 → 100644
View file @ 2ec3240f
/*
* Device tree sources for Exynos7 TMU sensor configuration
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <9>;
samsung,tmu_reference_voltage = <17>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <75>;
samsung,tmu_min_efuse_value = <15>;
samsung,tmu_max_efuse_value = <100>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi 0 → 100644
View file @ 2ec3240f
/*
* Device tree sources for default Exynos7 thermal zone definition
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
trips {
cpu-alert-0 {
temperature = <75000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-1 {
temperature = <80000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-2 {
temperature = <85000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-3 {
temperature = <90000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-4 {
temperature = <95000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-5 {
temperature = <100000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-alert-6 {
temperature = <110000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu-crit-0 {
temperature = <115000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file @ 2ec3240f
......@@ -27,6 +27,7 @@ aliases {
pinctrl6 = &pinctrl_fsys0;
pinctrl7 = &pinctrl_fsys1;
pinctrl8 = &pinctrl_bus1;
tmuctrl0 = &tmuctrl_0;
};
cpus {
......@@ -95,6 +96,35 @@ gic: interrupt-controller@11001000 {
<0x11006000 0x2000>;
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma0: pdma@10E10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10E10000 0x1000>;
interrupts = <0 225 0>;
clocks = <&clock_fsys0 ACLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@10EB0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10EB0000 0x1000>;
interrupts = <0 226 0>;
clocks = <&clock_fsys0 ACLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
clock_topc: clock-controller@10570000 {
compatible = "samsung,exynos7-clock-topc";
reg = <0x10570000 0x10000>;
......@@ -538,6 +568,25 @@ pwm: pwm@136c0000 {
clocks = <&clock_peric0 PCLK_PWM>;
clock-names = "timers";
};
tmuctrl_0: tmu@10060000 {
compatible = "samsung,exynos7-tmu";
reg = <0x10060000 0x200>;
interrupts = <0 108 0>;
clocks = <&clock_peris PCLK_TMU>,
<&clock_peris SCLK_TMU>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos7-tmu-sensor-conf.dtsi"
};
thermal-zones {
atlas_thermal: cluster0-thermal {
polling-delay-passive = <0>; /* milliseconds */
polling-delay = <0>; /* milliseconds */
thermal-sensors = <&tmuctrl_0>;
#include "exynos7-trip-points.dtsi"
};
};
};
};
......
arch/arm64/boot/dts/freescale/Makefile
View file @ 2ec3240f
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts 0 → 100644
View file @ 2ec3240f
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
};
fpga: board-control@2,0 {
compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
/* IRQ10_B */
interrupts = <0 150 0x4>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c512";
reg = <0x57>;
};
temp-sensor@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
};
};
};
&lpuart0 {
status = "okay";
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
};
};
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View file @ 2ec3240f
......@@ -107,6 +107,19 @@ cpld: board-control@2,0 {
};
};
&dspi0 {
bus-num = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
};
&duart0 {
status = "okay";
};
......
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file @ 2ec3240f
......@@ -171,6 +171,20 @@ ifc: ifc@1530000 {
interrupts = <0 43 0x4>;
};
qspi: quadspi@1550000 {
compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 99 0x4>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
big-endian;
status = "disabled";
};
esdhc: esdhc@1560000 {
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
......@@ -284,7 +298,7 @@ duart3: serial@21d0600 {
};
gpio1: gpio@2300000 {
compatible = "fsl,ls1043a-gpio";
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 0x4>;
gpio-controller;
......@@ -294,7 +308,7 @@ gpio1: gpio@2300000 {
};
gpio2: gpio@2310000 {
compatible = "fsl,ls1043a-gpio";
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 0x4>;
gpio-controller;
......@@ -304,7 +318,7 @@ gpio2: gpio@2310000 {
};
gpio3: gpio@2320000 {
compatible = "fsl,ls1043a-gpio";
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 68 0x4>;
gpio-controller;
......@@ -314,7 +328,7 @@ gpio3: gpio@2320000 {
};
gpio4: gpio@2330000 {
compatible = "fsl,ls1043a-gpio";
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 134 0x4>;
gpio-controller;
......
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View file @ 2ec3240f
......@@ -178,7 +178,14 @@ dflash2: en25s64 {
&qspi {
status = "okay";
qflash0: s25fl008k {
flash0: s25fl256s1@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
......
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ 2ec3240f
......@@ -265,6 +265,104 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
/*
* Define the maximum number of MACs present on the SoC.
*/
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
};
};
};
smmu: iommu@5000000 {
......@@ -318,7 +416,7 @@ smmu: iommu@5000000 {
dspi: dspi@2100000 {
status = "disabled";
compatible = "fsl,vf610-dspi";
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
......@@ -342,7 +440,7 @@ esdhc: esdhc@2140000 {
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
......@@ -353,7 +451,7 @@ gpio0: gpio@2300000 {
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
......@@ -364,7 +462,7 @@ gpio1: gpio@2310000 {
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
......@@ -375,7 +473,7 @@ gpio2: gpio@2320000 {
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
......@@ -444,7 +542,7 @@ ifc: ifc@2240000 {
qspi: quadspi@20c0000 {
status = "disabled";
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
......
arch/arm64/boot/dts/hisilicon/Makefile
View file @ 2ec3240f
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View file @ 2ec3240f
......@@ -6,11 +6,9 @@
*/
/dts-v1/;
/*Reserved 1MB memory for MCU*/
/memreserve/ 0x05e00000 0x00100000;
#include "hi6220.dtsi"
#include "hikey-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "HiKey Development Board";
......@@ -27,9 +25,201 @@ chosen {
stdout-path = "serial3:115200n8";
};
/*
* Reserve below regions from memory node:
*
* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
* 0x06df,f000 - 0x06df,ffff: Mailbox message data
* 0x0740,f000 - 0x0740,ffff: MCU firmware section
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
*/
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
<0x00000000 0x05f00000 0x00000000 0x00eff000>,
<0x00000000 0x06e00000 0x00000000 0x0060f000>,
<0x00000000 0x07410000 0x00000000 0x36bf0000>;
};
soc {
spi0: spi@f7106000 {
status = "ok";
};
i2c0: i2c@f7100000 {
status = "ok";
};
i2c1: i2c@f7101000 {
status = "ok";
};
uart1: uart@f7111000 {
status = "ok";
};
uart2: uart@f7112000 {
status = "ok";
};
uart3: uart@f7113000 {
status = "ok";
};
dwmmc_2: dwmmc2@f723f000 {
ti,non-removable;
non-removable;
/* WL_EN */
vmmc-supply = <&wlan_en_reg>;
#address-cells = <0x1>;
#size-cells = <0x0>;
wlcore: wlcore@2 {
compatible = "ti,wl1835";
reg = <2>; /* sdio func num */
/* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
};
wlan_en_reg: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* WLAN_EN GPIO */
gpio = <&gpio0 5 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
};
leds {
compatible = "gpio-leds";
user_led4 {
label = "user_led4";
gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
linux,default-trigger = "heartbeat";
};
user_led3 {
label = "user_led3";
gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
linux,default-trigger = "mmc0";
};
user_led2 {
label = "user_led2";
gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
linux,default-trigger = "mmc1";
};
user_led1 {
label = "user_led1";
gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
linux,default-trigger = "cpu0";
};
wlan_active_led {
label = "wifi_active";
gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "bt_active";
gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
linux,default-trigger = "hci0rx";
default-state = "off";
};
};
pmic: pmic@f8000000 {
compatible = "hisilicon,hi655x-pmic";
reg = <0x0 0xf8000000 0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
regulators {
ldo2: LDO2 {
regulator-name = "LDO2_2V8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3200000>;
regulator-enable-ramp-delay = <120>;
};
ldo7: LDO7 {
regulator-name = "LDO7_SDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <120>;
};
ldo10: LDO10 {
regulator-name = "LDO10_2V85";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <360>;
};
ldo13: LDO13 {
regulator-name = "LDO13_1V8";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-enable-ramp-delay = <120>;
};
ldo14: LDO14 {
regulator-name = "LDO14_2V8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3200000>;
regulator-enable-ramp-delay = <120>;
};
ldo15: LDO15 {
regulator-name = "LDO15_1V8";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
ldo17: LDO17 {
regulator-name = "LDO17_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3200000>;
regulator-enable-ramp-delay = <120>;
};
ldo19: LDO19 {
regulator-name = "LDO19_3V0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <360>;
};
ldo21: LDO21 {
regulator-name = "LDO21_1V8";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2000000>;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
ldo22: LDO22 {
regulator-name = "LDO22_1V2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
};
};
};
......
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file @ 2ec3240f
......@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi6220-clock.h>
#include <dt-bindings/pinctrl/hisi.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "hisilicon,hi6220";
......@@ -53,11 +55,42 @@ core3 {
};
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <700>;
exit-latency-us = <250>;
min-residency-us = <1000>;
};
CLUSTER_SLEEP: cluster-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cooling-min-level = <4>;
cooling-max-level = <0>;
#cooling-cells = <2>; /* min followed by max */
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <311>;
};
cpu1: cpu@1 {
......@@ -65,6 +98,9 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu2: cpu@2 {
......@@ -72,6 +108,9 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu3: cpu@3 {
......@@ -79,6 +118,9 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu4: cpu@100 {
......@@ -86,6 +128,9 @@ cpu4: cpu@100 {
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu5: cpu@101 {
......@@ -93,6 +138,9 @@ cpu5: cpu@101 {
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu6: cpu@102 {
......@@ -100,6 +148,9 @@ cpu6: cpu@102 {
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu7: cpu@103 {
......@@ -107,6 +158,48 @@ cpu7: cpu@103 {
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
};
};
cpu_opp_table: cpu_opp_table {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <500000>;
};
opp01 {
opp-hz = /bits/ 64 <432000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <500000>;
};
opp02 {
opp-hz = /bits/ 64 <729000000>;
opp-microvolt = <1090000>;
clock-latency-ns = <500000>;
};
opp03 {
opp-hz = /bits/ 64 <960000000>;
opp-microvolt = <1180000>;
clock-latency-ns = <500000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1330000>;
clock-latency-ns = <500000>;
};
};
......@@ -137,6 +230,11 @@ soc {
#size-cells = <2>;
ranges;
sram: sram@fff80000 {
compatible = "hisilicon,hi6220-sramctrl", "syscon";
reg = <0x0 0xfff80000 0x0 0x12000>;
};
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
......@@ -162,6 +260,14 @@ pm_ctrl: pm_ctrl@f7032000 {
#clock-cells = <1>;
};
stub_clock: stub_clock {
compatible = "hisilicon,hi6220-stub-clk";
hisilicon,hi6220-clk-sram = <&sram>;
#clock-cells = <1>;
mbox-names = "mbox-tx";
mboxes = <&mailbox 1 0 11>;
};
uart0: uart@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;
......@@ -178,6 +284,8 @@ uart1: uart@f7111000 {
clocks = <&sys_ctrl HI6220_UART1_PCLK>,
<&sys_ctrl HI6220_UART1_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
status = "disabled";
};
......@@ -188,6 +296,8 @@ uart2: uart@f7112000 {
clocks = <&sys_ctrl HI6220_UART2_PCLK>,
<&sys_ctrl HI6220_UART2_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
status = "disabled";
};
......@@ -198,6 +308,9 @@ uart3: uart@f7113000 {
clocks = <&sys_ctrl HI6220_UART3_PCLK>,
<&sys_ctrl HI6220_UART3_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
status = "disabled";
};
uart4: uart@f7114000 {
......@@ -207,7 +320,517 @@ uart4: uart@f7114000 {
clocks = <&sys_ctrl HI6220_UART4_PCLK>,
<&sys_ctrl HI6220_UART4_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
status = "disabled";
};
dual_timer0: timer@f8008000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xf8008000 0x0 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
<&ao_ctrl HI6220_TIMER0_PCLK>,
<&ao_ctrl HI6220_TIMER0_PCLK>;
clock-names = "timer1", "timer2", "apb_pclk";
};
pmx0: pinmux@f7010000 {
compatible = "pinctrl-single";
reg = <0x0 0xf7010000 0x0 0x27c>;
#address-cells = <1>;
#size-cells = <1>;
#gpio-range-cells = <3>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
pinctrl-single,gpio-range = <
&range 80 8 MUX_M0 /* gpio 3: [0..7] */
&range 88 8 MUX_M0 /* gpio 4: [0..7] */
&range 96 8 MUX_M0 /* gpio 5: [0..7] */
&range 104 8 MUX_M0 /* gpio 6: [0..7] */
&range 112 8 MUX_M0 /* gpio 7: [0..7] */
&range 120 2 MUX_M0 /* gpio 8: [0..1] */
&range 2 6 MUX_M1 /* gpio 8: [2..7] */
&range 8 8 MUX_M1 /* gpio 9: [0..7] */
&range 0 1 MUX_M1 /* gpio 10: [0] */
&range 16 7 MUX_M1 /* gpio 10: [1..7] */
&range 23 3 MUX_M1 /* gpio 11: [0..2] */
&range 28 5 MUX_M1 /* gpio 11: [3..7] */
&range 33 3 MUX_M1 /* gpio 12: [0..2] */
&range 43 5 MUX_M1 /* gpio 12: [3..7] */
&range 48 8 MUX_M1 /* gpio 13: [0..7] */
&range 56 8 MUX_M1 /* gpio 14: [0..7] */
&range 74 6 MUX_M1 /* gpio 15: [0..5] */
&range 122 1 MUX_M1 /* gpio 15: [6] */
&range 126 1 MUX_M1 /* gpio 15: [7] */
&range 127 8 MUX_M1 /* gpio 16: [0..7] */
&range 135 8 MUX_M1 /* gpio 17: [0..7] */
&range 143 8 MUX_M1 /* gpio 18: [0..7] */
&range 151 8 MUX_M1 /* gpio 19: [0..7] */
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@f7010800 {
compatible = "pinconf-single";
reg = <0x0 0xf7010800 0x0 0x28c>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
};
pmx2: pinmux@f8001800 {
compatible = "pinconf-single";
reg = <0x0 0xf8001800 0x0 0x78>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
};
gpio0: gpio@f8011000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8011000 0x0 0x1000>;
interrupts = <0 52 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio1: gpio@f8012000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8012000 0x0 0x1000>;
interrupts = <0 53 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio2: gpio@f8013000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8013000 0x0 0x1000>;
interrupts = <0 54 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio3: gpio@f8014000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8014000 0x0 0x1000>;
interrupts = <0 55 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 80 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio4: gpio@f7020000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7020000 0x0 0x1000>;
interrupts = <0 56 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 88 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio5: gpio@f7021000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7021000 0x0 0x1000>;
interrupts = <0 57 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 96 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio6: gpio@f7022000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7022000 0x0 0x1000>;
interrupts = <0 58 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 104 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio7: gpio@f7023000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7023000 0x0 0x1000>;
interrupts = <0 59 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 112 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio8: gpio@f7024000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7024000 0x0 0x1000>;
interrupts = <0 60 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio9: gpio@f7025000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7025000 0x0 0x1000>;
interrupts = <0 61 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 8 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio10: gpio@f7026000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7026000 0x0 0x1000>;
interrupts = <0 62 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio11: gpio@f7027000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7027000 0x0 0x1000>;
interrupts = <0 63 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio12: gpio@f7028000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7028000 0x0 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio13: gpio@f7029000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7029000 0x0 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 48 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio14: gpio@f702a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702a000 0x0 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 56 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio15: gpio@f702b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702b000 0x0 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <
&pmx0 0 74 6
&pmx0 6 122 1
&pmx0 7 126 1
>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio16: gpio@f702c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702c000 0x0 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 127 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio17: gpio@f702d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702d000 0x0 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 135 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio18: gpio@f702e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702e000 0x0 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 143 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio19: gpio@f702f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702f000 0x0 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 151 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
spi0: spi@f7106000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xf7106000 0x0 0x1000>;
interrupts = <0 50 4>;
bus-id = <0>;
enable-dma = <0>;
clocks = <&sys_ctrl HI6220_SPI_CLK>;
clock-names = "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
num-cs = <1>;
cs-gpios = <&gpio6 2 0>;
status = "disabled";
};
i2c0: i2c@f7100000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xf7100000 0x0 0x1000>;
interrupts = <0 44 4>;
clocks = <&sys_ctrl HI6220_I2C0_CLK>;
i2c-sda-hold-time-ns = <300>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
status = "disabled";
};
i2c1: i2c@f7101000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xf7101000 0x0 0x1000>;
clocks = <&sys_ctrl HI6220_I2C1_CLK>;
interrupts = <0 45 4>;
i2c-sda-hold-time-ns = <300>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
status = "disabled";
};
i2c2: i2c@f7102000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xf7102000 0x0 0x1000>;
clocks = <&sys_ctrl HI6220_I2C2_CLK>;
interrupts = <0 46 4>;
i2c-sda-hold-time-ns = <300>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
status = "disabled";
};
fixed_5v_hub: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed_5v_hub";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
gpio = <&gpio0 7 0>;
regulator-always-on;
};
usb_phy: usbphy {
compatible = "hisilicon,hi6220-usb-phy";
#phy-cells = <0>;
phy-supply = <&fixed_5v_hub>;
hisilicon,peripheral-syscon = <&sys_ctrl>;
};
usb: usb@f72c0000 {
compatible = "hisilicon,hi6220-usb";
reg = <0x0 0xf72c0000 0x0 0x40000>;
phys = <&usb_phy>;
phy-names = "usb2-phy";
clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
clock-names = "otg";
dr_mode = "otg";
g-use-dma;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 128 128 128 128>;
interrupts = <0 77 0x4>;
};
mailbox: mailbox@f7510000 {
compatible = "hisilicon,hi6220-mbox";
reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
<0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <3>;
};
dwmmc_0: dwmmc0@f723d000 {
compatible = "hisilicon,hi6220-dw-mshc";
num-slots = <0x1>;
cap-mmc-highspeed;
non-removable;
reg = <0x0 0xf723d000 0x0 0x1000>;
interrupts = <0x0 0x48 0x4>;
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
&emmc_cfg_func &emmc_rst_cfg_func>;
};
dwmmc_1: dwmmc1@f723e000 {
compatible = "hisilicon,hi6220-dw-mshc";
num-slots = <0x1>;
card-detect-delay = <200>;
hisilicon,peripheral-syscon = <&ao_ctrl>;
cap-sd-highspeed;
reg = <0x0 0xf723e000 0x0 0x1000>;
interrupts = <0x0 0x49 0x4>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
vqmmc-supply = <&ldo7>;
vmmc-supply = <&ldo10>;
bus-width = <0x4>;
disable-wp;
cd-gpios = <&gpio1 0 1>;
pinctrl-names = "default", "idle";
pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
};
dwmmc_2: dwmmc2@f723f000 {
compatible = "hisilicon,hi6220-dw-mshc";
num-slots = <0x1>;
reg = <0x0 0xf723f000 0x0 0x1000>;
interrupts = <0x0 0x4a 0x4>;
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
clock-names = "ciu", "biu";
bus-width = <0x4>;
broken-cd;
pinctrl-names = "default", "idle";
pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
};
tsensor: tsensor@0,f7030700 {
compatible = "hisilicon,tsensor";
reg = <0x0 0xf7030700 0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl 22>;
clock-names = "thermal_clk";
#thermal-sensor-cells = <1>;
};
thermal-zones {
cls0: cls0 {
polling-delay = <1000>;
polling-delay-passive = <100>;
sustainable-power = <3326>;
/* sensor ID */
thermal-sensors = <&tsensor 2>;
trips {
threshold: trip-point@0 {
temperature = <65000>;
hysteresis = <0>;
type = "passive";
};
target: trip-point@1 {
temperature = <75000>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
};
arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi 0 → 100644
View file @ 2ec3240f
/*
* pinctrl dts fils for Hislicon HiKey development board
*
*/
#include <dt-bindings/pinctrl/hisi.h>
/ {
soc {
pmx0: pinmux@f7010000 {
pinctrl-names = "default";
pinctrl-0 = <
&boot_sel_pmx_func
&hkadc_ssi_pmx_func
&codec_clk_pmx_func
&pwm_in_pmx_func
&bl_pwm_pmx_func
>;
boot_sel_pmx_func: boot_sel_pmx_func {
pinctrl-single,pins = <
0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
>;
};
emmc_pmx_func: emmc_pmx_func {
pinctrl-single,pins = <
0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
>;
};
sd_pmx_func: sd_pmx_func {
pinctrl-single,pins = <
0xc MUX_M0 /* SD_CLK (IOMG003) */
0x10 MUX_M0 /* SD_CMD (IOMG004) */
0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
>;
};
sd_pmx_idle: sd_pmx_idle {
pinctrl-single,pins = <
0xc MUX_M1 /* SD_CLK (IOMG003) */
0x10 MUX_M1 /* SD_CMD (IOMG004) */
0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
>;
};
sdio_pmx_func: sdio_pmx_func {
pinctrl-single,pins = <
0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
>;
};
sdio_pmx_idle: sdio_pmx_idle {
pinctrl-single,pins = <
0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
>;
};
isp_pmx_func: isp_pmx_func {
pinctrl-single,pins = <
0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
0x38 MUX_M1 /* ISP_PWM (IOMG014) */
0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
>;
};
hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
pinctrl-single,pins = <
0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
>;
};
codec_clk_pmx_func: codec_clk_pmx_func {
pinctrl-single,pins = <
0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
>;
};
codec_pmx_func: codec_pmx_func {
pinctrl-single,pins = <
0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
0x78 MUX_M0 /* CODEC_DI (IOMG030) */
0x7c MUX_M0 /* CODEC_DO (IOMG031) */
>;
};
fm_pmx_func: fm_pmx_func {
pinctrl-single,pins = <
0x80 MUX_M1 /* FM_XCLK (IOMG032) */
0x84 MUX_M1 /* FM_XFS (IOMG033) */
0x88 MUX_M1 /* FM_DI (IOMG034) */
0x8c MUX_M1 /* FM_DO (IOMG035) */
>;
};
bt_pmx_func: bt_pmx_func {
pinctrl-single,pins = <
0x90 MUX_M0 /* BT_XCLK (IOMG036) */
0x94 MUX_M0 /* BT_XFS (IOMG037) */
0x98 MUX_M0 /* BT_DI (IOMG038) */
0x9c MUX_M0 /* BT_DO (IOMG039) */
>;
};
pwm_in_pmx_func: pwm_in_pmx_func {
pinctrl-single,pins = <
0xb8 MUX_M1 /* PWM_IN (IOMG046) */
>;
};
bl_pwm_pmx_func: bl_pwm_pmx_func {
pinctrl-single,pins = <
0xbc MUX_M1 /* BL_PWM (IOMG047) */
>;
};
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
>;
};
uart1_pmx_func: uart1_pmx_func {
pinctrl-single,pins = <
0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
0x188 MUX_M1 /* UART3_RXD (IOMG098) */
0x18c MUX_M1 /* UART3_TXD (IOMG099) */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
>;
};
uart5_pmx_func: uart5_pmx_func {
pinctrl-single,pins = <
0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
0xec MUX_M0 /* I2C0_SDA (IOMG059) */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
>;
};
spi0_pmx_func: spi0_pmx_func {
pinctrl-single,pins = <
0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
>;
};
};
pmx1: pinmux@f7010800 {
pinctrl-names = "default";
pinctrl-0 = <
&boot_sel_cfg_func
&hkadc_ssi_cfg_func
&codec_clk_cfg_func
&pwm_in_cfg_func
&bl_pwm_cfg_func
>;
boot_sel_cfg_func: boot_sel_cfg_func {
pinctrl-single,pins = <
0x0 0x0 /* BOOT_SEL (IOCFG000) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
pinctrl-single,pins = <
0x6c 0x0 /* HKADC_SSI (IOCFG027) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
emmc_clk_cfg_func: emmc_clk_cfg_func {
pinctrl-single,pins = <
0x104 0x0 /* EMMC_CLK (IOCFG065) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
emmc_cfg_func: emmc_cfg_func {
pinctrl-single,pins = <
0x108 0x0 /* EMMC_CMD (IOCFG066) */
0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
emmc_rst_cfg_func: emmc_rst_cfg_func {
pinctrl-single,pins = <
0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
0xc 0x0 /* SD_CLK (IOCFG003) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
};
sd_clk_cfg_idle: sd_clk_cfg_idle {
pinctrl-single,pins = <
0xc 0x0 /* SD_CLK (IOCFG003) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
sd_cfg_func: sd_cfg_func {
pinctrl-single,pins = <
0x10 0x0 /* SD_CMD (IOCFG004) */
0x14 0x0 /* SD_DATA0 (IOCFG005) */
0x18 0x0 /* SD_DATA1 (IOCFG006) */
0x1c 0x0 /* SD_DATA2 (IOCFG007) */
0x20 0x0 /* SD_DATA3 (IOCFG008) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
sd_cfg_idle: sd_cfg_idle {
pinctrl-single,pins = <
0x10 0x0 /* SD_CMD (IOCFG004) */
0x14 0x0 /* SD_DATA0 (IOCFG005) */
0x18 0x0 /* SD_DATA1 (IOCFG006) */
0x1c 0x0 /* SD_DATA2 (IOCFG007) */
0x20 0x0 /* SD_DATA3 (IOCFG008) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
0x134 0x0 /* SDIO_CLK (IOCFG077) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
sdio_clk_cfg_idle: sdio_clk_cfg_idle {
pinctrl-single,pins = <
0x134 0x0 /* SDIO_CLK (IOCFG077) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x138 0x0 /* SDIO_CMD (IOCFG078) */
0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
sdio_cfg_idle: sdio_cfg_idle {
pinctrl-single,pins = <
0x138 0x0 /* SDIO_CMD (IOCFG078) */
0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
isp_cfg_func1: isp_cfg_func1 {
pinctrl-single,pins = <
0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
0x3c 0x0 /* ISP_PWM (IOCFG015) */
0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
0x58 0x0 /* ISP_SDA0 (IOCFG022) */
0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
0x60 0x0 /* ISP_SDA1 (IOCFG024) */
0x64 0x0 /* ISP_SCL1 (IOCFG025) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
isp_cfg_idle1: isp_cfg_idle1 {
pinctrl-single,pins = <
0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
isp_cfg_func2: isp_cfg_func2 {
pinctrl-single,pins = <
0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
codec_clk_cfg_func: codec_clk_cfg_func {
pinctrl-single,pins = <
0x70 0x0 /* CODEC_CLK (IOCFG028) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
codec_clk_cfg_idle: codec_clk_cfg_idle {
pinctrl-single,pins = <
0x70 0x0 /* CODEC_CLK (IOCFG028) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
codec_cfg_func1: codec_cfg_func1 {
pinctrl-single,pins = <
0x74 0x0 /* DMIC_CLK (IOCFG029) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
codec_cfg_func2: codec_cfg_func2 {
pinctrl-single,pins = <
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
0x7c 0x0 /* CODEC_DI (IOCFG031) */
0x80 0x0 /* CODEC_DO (IOCFG032) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
codec_cfg_idle2: codec_cfg_idle2 {
pinctrl-single,pins = <
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
0x7c 0x0 /* CODEC_DI (IOCFG031) */
0x80 0x0 /* CODEC_DO (IOCFG032) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
fm_cfg_func: fm_cfg_func {
pinctrl-single,pins = <
0x84 0x0 /* FM_XCLK (IOCFG033) */
0x88 0x0 /* FM_XFS (IOCFG034) */
0x8c 0x0 /* FM_DI (IOCFG035) */
0x90 0x0 /* FM_DO (IOCFG036) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
bt_cfg_func: bt_cfg_func {
pinctrl-single,pins = <
0x94 0x0 /* BT_XCLK (IOCFG037) */
0x98 0x0 /* BT_XFS (IOCFG038) */
0x9c 0x0 /* BT_DI (IOCFG039) */
0xa0 0x0 /* BT_DO (IOCFG040) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
bt_cfg_idle: bt_cfg_idle {
pinctrl-single,pins = <
0x94 0x0 /* BT_XCLK (IOCFG037) */
0x98 0x0 /* BT_XFS (IOCFG038) */
0x9c 0x0 /* BT_DI (IOCFG039) */
0xa0 0x0 /* BT_DO (IOCFG040) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
pwm_in_cfg_func: pwm_in_cfg_func {
pinctrl-single,pins = <
0xbc 0x0 /* PWM_IN (IOCFG047) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
bl_pwm_cfg_func: bl_pwm_cfg_func {
pinctrl-single,pins = <
0xc0 0x0 /* BL_PWM (IOCFG048) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart0_cfg_func1: uart0_cfg_func1 {
pinctrl-single,pins = <
0xc4 0x0 /* UART0_RXD (IOCFG049) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart0_cfg_func2: uart0_cfg_func2 {
pinctrl-single,pins = <
0xc8 0x0 /* UART0_TXD (IOCFG050) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
uart1_cfg_func1: uart1_cfg_func1 {
pinctrl-single,pins = <
0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
0xd4 0x0 /* UART1_RXD (IOCFG053) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart1_cfg_func2: uart1_cfg_func2 {
pinctrl-single,pins = <
0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
0xd8 0x0 /* UART1_TXD (IOCFG054) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart2_cfg_func: uart2_cfg_func {
pinctrl-single,pins = <
0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
0xe4 0x0 /* UART2_RXD (IOCFG057) */
0xe8 0x0 /* UART2_TXD (IOCFG058) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart3_cfg_func: uart3_cfg_func {
pinctrl-single,pins = <
0x190 0x0 /* UART3_CTS_N (IOCFG100) */
0x194 0x0 /* UART3_RTS_N (IOCFG101) */
0x198 0x0 /* UART3_RXD (IOCFG102) */
0x19c 0x0 /* UART3_TXD (IOCFG103) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart4_cfg_func: uart4_cfg_func {
pinctrl-single,pins = <
0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
0x1e8 0x0 /* UART4_RXD (IOCFG122) */
0x1ec 0x0 /* UART4_TXD (IOCFG123) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
uart5_cfg_func: uart5_cfg_func {
pinctrl-single,pins = <
0x1d8 0x0 /* UART4_RXD (IOCFG118) */
0x1dc 0x0 /* UART4_TXD (IOCFG119) */
>;
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0xec 0x0 /* I2C0_SCL (IOCFG059) */
0xf0 0x0 /* I2C0_SDA (IOCFG060) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
i2c1_cfg_func: i2c1_cfg_func {
pinctrl-single,pins = <
0xf4 0x0 /* I2C1_SCL (IOCFG061) */
0xf8 0x0 /* I2C1_SDA (IOCFG062) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
i2c2_cfg_func: i2c2_cfg_func {
pinctrl-single,pins = <
0xfc 0x0 /* I2C2_SCL (IOCFG063) */
0x100 0x0 /* I2C2_SDA (IOCFG064) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
spi0_cfg_func: spi0_cfg_func {
pinctrl-single,pins = <
0x1b0 0x0 /* SPI0_DI (IOCFG108) */
0x1b4 0x0 /* SPI0_DO (IOCFG109) */
0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
};
pmx2: pinmux@f8001800 {
pinctrl-names = "default";
pinctrl-0 = <
&rstout_n_cfg_func
>;
rstout_n_cfg_func: rstout_n_cfg_func {
pinctrl-single,pins = <
0x0 0x0 /* RSTOUT_N (IOCFG000) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
pinctrl-single,pins = <
0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
sysclk0_en_cfg_func: sysclk0_en_cfg_func {
pinctrl-single,pins = <
0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
jtag_tdo_cfg_func: jtag_tdo_cfg_func {
pinctrl-single,pins = <
0xc 0x0 /* JTAG_TDO (IOCFG003) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
rf_reset_cfg_func: rf_reset_cfg_func {
pinctrl-single,pins = <
0x70 0x0 /* RF_RESET0 (IOCFG028) */
0x74 0x0 /* RF_RESET1 (IOCFG029) */
>;
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
};
};
};
arch/arm64/boot/dts/hisilicon/hip05-d02.dts
View file @ 2ec3240f
......@@ -52,3 +52,37 @@ &uart0 {
&peri_gpio0 {
status = "ok";
};
&lbc {
status = "ok";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x90000000 0x08000000>,
<1 0 0x0 0x98000000 0x08000000>;
nor-flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "numonyx,js28f00a", "cfi-flash";
reg = <0 0x0 0x08000000>;
bank-width = <2>;
/* The three parts may not used */
partition@0 {
label = "BIOS";
reg = <0x0 0x300000>;
};
partition@300000 {
label = "Linux";
reg = <0x300000 0xa00000>;
};
partition@1000000 {
label = "Rootfs";
reg = <0x01000000 0x02000000>;
};
};
cpld@1,0 {
compatible = "hisilicon,hip05-cpld";
reg = <1 0x0 0x100>;
};
};
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View file @ 2ec3240f
......@@ -249,24 +249,28 @@ gic: interrupt-controller@8d000000 {
its_peri: interrupt-controller@8c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x8c000000 0x0 0x40000>;
};
its_m3: interrupt-controller@a3000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xa3000000 0x0 0x40000>;
};
its_pcie: interrupt-controller@b7000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xb7000000 0x0 0x40000>;
};
its_dsa: interrupt-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
};
......@@ -323,6 +327,12 @@ uart1: uart@80310000 {
status = "disabled";
};
lbc: localbus@80380000 {
compatible = "hisilicon,hisi-localbus", "simple-bus";
reg = <0x0 0x80380000 0x0 0x10000>;
status = "disabled";
};
peri_gpio0: gpio@802e0000 {
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/hisilicon/hip06-d03.dts 0 → 100644
View file @ 2ec3240f
/**
* dts file for Hisilicon D03 Development Board
*
* Copyright (C) 2016 Hisilicon Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
/dts-v1/;
#include "hip06.dtsi"
/ {
model = "Hisilicon Hip06 D03 Development Board";
compatible = "hisilicon,hip06-d03";
memory@00000000 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
chosen { };
};
&usb_ohci {
status = "ok";
};
&usb_ehci {
status = "ok";
};
arch/arm64/boot/dts/hisilicon/hip06.dtsi 0 → 100644
View file @ 2ec3240f
/**
* dts file for Hisilicon D03 Development Board
*
* Copyright (C) 2016 Hisilicon Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "hisilicon,hip06-d03";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
cluster2 {
core0 {
cpu = <&cpu8>;
};
core1 {
cpu = <&cpu9>;
};
core2 {
cpu = <&cpu10>;
};
core3 {
cpu = <&cpu11>;
};
};
cluster3 {
core0 {
cpu = <&cpu12>;
};
core1 {
cpu = <&cpu13>;
};
core2 {
cpu = <&cpu14>;
};
core3 {
cpu = <&cpu15>;
};
};
};
cpu0: cpu@10000 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10000>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu1: cpu@10001 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10001>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu2: cpu@10002 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10002>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu3: cpu@10003 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10003>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu4: cpu@10100 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu5: cpu@10101 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu6: cpu@10102 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10102>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu7: cpu@10103 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10103>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu8: cpu@10200 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10200>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu9: cpu@10201 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10201>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu10: cpu@10202 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10202>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu11: cpu@10203 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10203>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu12: cpu@10300 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10300>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu13: cpu@10301 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10301>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu14: cpu@10302 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10302>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu15: cpu@10303 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x10303>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};
gic: interrupt-controller@4d000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x30000>;
reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
<0x0 0x4d100000 0 0x300000>, /* GICR */
<0x0 0xfe000000 0 0x10000>, /* GICC */
<0x0 0xfe010000 0 0x10000>, /* GICH */
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its_dsa: interrupt-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
mbigen_pcie@a0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa0080000 0x0 0x10000>;
mbigen_usb: intc_usb {
msi-parent = <&its_dsa 0x40080>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <2>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb_ohci: ohci@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <64 4>;
dma-coherent;
status = "disabled";
};
usb_ehci: ehci@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <65 4>;
dma-coherent;
status = "disabled";
};
};
};
arch/arm64/boot/dts/lg/Makefile 0 → 100644
View file @ 2ec3240f
dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb
arch/arm64/boot/dts/lg/lg1312-ref.dts 0 → 100644
View file @ 2ec3240f
/*
* dts file for lg1312 Reference Board.
*
* Copyright (C) 2016, LG Electronics
*/
/dts-v1/;
#include "lg1312.dtsi"
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "LG Electronics, DTV SoC LG1312 Reference Board";
compatible = "lge,lg1312-ref", "lge,lg1312";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
memory {
device_type = "memory";
reg = <0x0 0x00000000 0x20000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
arch/arm64/boot/dts/lg/lg1312.dtsi 0 → 100644
View file @ 2ec3240f
/*
* dts file for lg1312 SoC
*
* Copyright (C) 2016, LG Electronics
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "lge,lg1312";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
gic: interrupt-controller@c0001000 {
#interrupt-cells = <3>;
compatible = "arm,gic-400";
interrupt-controller;
reg = <0x0 0xc0001000 0x1000>,
<0x0 0xc0002000 0x2000>,
<0x0 0xc0004000 0x2000>,
<0x0 0xc0006000 0x2000>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>;
};
clk_bus: clk_bus {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <198000000>;
clock-output-names = "BUSCLK";
};
soc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
eth0: ethernet@c1b00000 {
compatible = "cdns,gem";
reg = <0x0 0xc1b00000 0x1000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "hclk", "pclk";
phy-mode = "rmii";
/* Filled in by boot */
mac-address = [ 00 00 00 00 00 00 ];
};
};
amba {
#address-cells = <2>;
#size-cells = <1>;
#interrupts-cells = <3>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges;
timers: timer@fd100000 {
compatible = "arm,sp804";
reg = <0x0 0xfd100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xfd200000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe000000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
uart1: serial@fe100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe100000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
uart2: serial@fe200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe200000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
spi0: ssp@fe800000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe800000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
spi1: ssp@fe900000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe900000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
dmac0: dma@c1128000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xc1128000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio0: gpio@fd400000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd400000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio1: gpio@fd410000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd410000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio2: gpio@fd420000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd420000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio3: gpio@fd430000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd430000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio4: gpio@fd440000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd440000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio5: gpio@fd450000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd450000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio6: gpio@fd460000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd460000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio7: gpio@fd470000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd470000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio8: gpio@fd480000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd480000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio9: gpio@fd490000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd490000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio10: gpio@fd4a0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4a0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio11: gpio@fd4b0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4b0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio12: gpio@fd4c0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4c0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio13: gpio@fd4d0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4d0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio14: gpio@fd4e0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4e0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio15: gpio@fd4f0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4f0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio16: gpio@fd500000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd500000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio17: gpio@fd510000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd510000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
};
};
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View file @ 2ec3240f
......@@ -60,27 +60,19 @@ memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
};
soc {
internal-regs {
/*
* Exported on the micro USB connector CON32
* through an FTDI
*/
uart0: serial@12000 {
status = "okay";
};
/* CON31 */
usb3@58000 {
status = "okay";
};
/* CON3 */
&sata {
status = "okay";
};
/* CON3 */
sata@e0000 {
status = "okay";
};
};
};
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
status = "okay";
};
/* CON31 */
&usb3 {
status = "okay";
};
arch/arm64/boot/dts/marvell/armada-372x.dtsi
View file @ 2ec3240f
......@@ -59,5 +59,4 @@ cpu@1 {
enable-method = "psci";
};
};
};
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file @ 2ec3240f
......@@ -105,14 +105,28 @@ uart0: serial@12000 {
status = "disabled";
};
usb3@58000 {
compatible = "generic-xhci";
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sata@e0000 {
xor@60900 {
compatible = "marvell,armada-3700-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
xor10 {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
xor11 {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm64/boot/dts/marvell/armada-7020.dtsi
View file @ 2ec3240f
......@@ -46,6 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
#include "armada-cp110-master.dtsi"
/ {
model = "Marvell Armada 7020";
......
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View file @ 2ec3240f
......@@ -51,42 +51,98 @@ / {
compatible = "marvell,armada7040-db", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
ap806 {
config-space {
spi@510600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <10000000>;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xce0000>;
};
};
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xce0000>;
};
};
};
};
&uart0 {
status = "okay";
};
i2c@511000 {
status = "okay";
clock-frequency = <100000>;
&cpm_pcie2 {
status = "okay";
};
&cpm_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&cpm_spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x200000>;
};
serial@512000 {
status = "okay";
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xe00000>;
};
};
};
};
&cpm_sata0 {
status = "okay";
};
&cpm_usb3_0 {
status = "okay";
};
&cpm_usb3_1 {
status = "okay";
};
arch/arm64/boot/dts/marvell/armada-7040.dtsi
View file @ 2ec3240f
......@@ -46,6 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
/ {
model = "Marvell Armada 7040";
......
arch/arm64/boot/dts/marvell/armada-8020.dtsi
View file @ 2ec3240f
......@@ -46,6 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
#include "armada-cp110-master.dtsi"
/ {
model = "Marvell Armada 8020";
......
arch/arm64/boot/dts/marvell/armada-8040.dtsi
View file @ 2ec3240f
......@@ -46,6 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
/ {
model = "Marvell Armada 8040";
......
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View file @ 2ec3240f
......@@ -79,6 +79,4 @@ cpu@101 {
enable-method = "psci";
};
};
};
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file @ 2ec3240f
......@@ -54,12 +54,16 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;
......@@ -136,7 +140,7 @@ odmi: odmi@300000 {
marvell,spi-base = <128>, <136>, <144>, <152>;
};
xor0@400000 {
xor@400000 {
compatible = "marvell,mv-xor-v2";
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
......@@ -144,7 +148,7 @@ xor0@400000 {
dma-coherent;
};
xor1@420000 {
xor@420000 {
compatible = "marvell,mv-xor-v2";
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
......@@ -152,7 +156,7 @@ xor1@420000 {
dma-coherent;
};
xor2@440000 {
xor@440000 {
compatible = "marvell,mv-xor-v2";
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
......@@ -160,7 +164,7 @@ xor2@440000 {
dma-coherent;
};
xor3@460000 {
xor@460000 {
compatible = "marvell,mv-xor-v2";
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
......@@ -175,63 +179,51 @@ spi0: spi@510600 {
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ringclk 2>;
clocks = <&ap_syscon 3>;
status = "disabled";
};
i2c0: i2c@511000 {
compatible = "marvell,mv64xxx-i2c";
compatible = "marvell,mv78230-i2c";
reg = <0x511000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&ringclk 2>;
clocks = <&ap_syscon 3>;
status = "disabled";
};
serial@512000 {
uart0: serial@512000 {
compatible = "snps,dw-apb-uart";
reg = <0x512000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ringclk 2>;
clocks = <&ap_syscon 3>;
status = "disabled";
};
serial@512100 {
uart1: serial@512100 {
compatible = "snps,dw-apb-uart";
reg = <0x512100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ringclk 2>;
clocks = <&ap_syscon 3>;
status = "disabled";
};
dfx-server@6f8000 {
compatible = "simple-mfd", "syscon";
reg = <0x6f8000 0x70000>;
coreclk: clk@204 {
compatible = "marvell,armada-ap806-core-clock";
#clock-cells = <1>;
clock-output-names = "ddr", "ring", "cpu";
};
ringclk: clk@250 {
compatible = "marvell,armada-ap806-ring-clock";
#clock-cells = <1>;
clock-output-names = "ring-0", "ring-2",
"ring-3", "ring-4",
"ring-5";
clocks = <&coreclk 1>;
};
ap_syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";
#clock-cells = <1>;
clock-output-names = "ap-cpu-cluster-0",
"ap-cpu-cluster-1",
"ap-fixed", "ap-mss";
reg = <0x6f4000 0x1000>;
};
};
};
};
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi 0 → 100644
View file @ 2ec3240f
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for Marvell Armada CP110 Master.
*/
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
config-space {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
reg = <0x440000 0x1000>;
#clock-cells = <2>;
core-clock-output-names =
"cpm-apll", "cpm-ppv2-core", "cpm-eip",
"cpm-core", "cpm-nand-core";
gate-clock-output-names =
"cpm-audio", "cpm-communit", "cpm-nand",
"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
"cpm-mg-core", "cpm-xor1", "cpm-xor0",
"cpm-gop-dp", "none", "cpm-pcie_x10",
"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata", "cpm-sata-usb", "cpm-main",
"cpm-sd-mmc", "none", "none",
"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci";
reg = <0x540000 0x30000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 15>;
status = "disabled";
};
cpm_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 22>;
status = "disabled";
};
cpm_usb3_1: usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 23>;
status = "disabled";
};
cpm_spi0: spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
clocks = <&cpm_syscon0 0 3>;
status = "disabled";
};
cpm_spi1: spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
cpm_i2c0: i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
cpm_i2c1: i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
};
cpm_pcie0: pcie@f2600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2600000 0 0x10000>,
<0 0xf6f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
status = "disabled";
};
cpm_pcie1: pcie@f2620000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2620000 0 0x10000>,
<0 0xf7f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 11>;
status = "disabled";
};
cpm_pcie2: pcie@f2640000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2640000 0 0x10000>,
<0 0xf8f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 12>;
status = "disabled";
};
};
};
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file @ 2ec3240f
......@@ -125,6 +125,49 @@ cpum_ck: oscillator@2 {
clock-output-names = "cpum_ck";
};
thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&thermal>;
sustainable-power = <1500>; /* milliwatts */
trips {
threshold: trip-point@0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point@1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit@0 {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map@0 {
trip = <&target>;
cooling-device = <&cpu0 0 0>;
contribution = <1024>;
};
map@1 {
trip = <&target>;
cooling-device = <&cpu2 0 0>;
contribution = <2048>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
......@@ -313,6 +356,11 @@ gic: interrupt-controller@10220000 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
auxadc: auxadc@11001000 {
compatible = "mediatek,mt8173-auxadc";
reg = <0 0x11001000 0 0x1000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
......@@ -414,6 +462,18 @@ spi: spi@1100a000 {
status = "disabled";
};
thermal: thermal@1100b000 {
#thermal-sensor-cells = <0>;
compatible = "mediatek,mt8173-thermal";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
};
nor_flash: spi@1100d000 {
compatible = "mediatek,mt8173-nor";
reg = <0 0x1100d000 0 0xe0>;
......
arch/arm64/boot/dts/nvidia/Makefile
View file @ 2ec3240f
......@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
View file @ 2ec3240f
......@@ -8,19 +8,22 @@ / {
compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
aliases {
rtc0 = "/i2c@0,7000d000/as3722@40";
rtc1 = "/rtc@0,7000e000";
rtc0 = "/i2c@7000d000/as3722@40";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
chosen { };
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
host1x@0,50000000 {
hdmi@0,54280000 {
host1x@50000000 {
hdmi@54280000 {
status = "disabled";
vdd-supply = <&vdd_3v3_hdmi>;
......@@ -32,26 +35,26 @@ hdmi@0,54280000 {
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
sor@0,54540000 {
sor@54540000 {
status = "okay";
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
dpaux: dpaux@0,545c0000 {
dpaux: dpaux@545c0000 {
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
};
};
gpu@0,57000000 {
gpu@57000000 {
status = "okay";
vdd-supply = <&vdd_gpu>;
};
pinmux@0,70000868 {
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
......@@ -523,21 +526,21 @@ soc_warm_reset_l {
};
};
serial@0,70006000 {
serial@70006000 {
status = "okay";
};
pwm: pwm@0,7000a000 {
pwm: pwm@7000a000 {
status = "okay";
};
/* HDMI DDC */
hdmi_ddc: i2c@0,7000c700 {
hdmi_ddc: i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
......@@ -744,7 +747,7 @@ ldo11 {
};
};
spi@0,7000d400 {
spi@7000d400 {
status = "okay";
ec: cros-ec@0 {
......@@ -876,7 +879,7 @@ MATRIX_KEY(0x07, 0x0b, KEY_UP)
};
};
pmc@0,7000e400 {
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
#wake-cells = <3>;
......@@ -890,12 +893,12 @@ pmc@0,7000e400 {
};
/* WIFI/BT module */
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "disabled";
};
/* external SD/MMC */
sdhci@0,700b0400 {
sdhci@700b0400 {
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
......@@ -905,35 +908,35 @@ sdhci@0,700b0400 {
};
/* EMMC 4.51 */
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@0,7d000000 {
usb@7d000000 {
status = "okay";
};
usb-phy@0,7d000000 {
usb-phy@7d000000 {
status = "okay";
vbus-supply = <&vdd_usb1_vbus>;
};
usb@0,7d004000 {
usb@7d004000 {
status = "okay";
};
usb-phy@0,7d004000 {
usb-phy@7d004000 {
status = "okay";
vbus-supply = <&vdd_run_cam>;
};
usb@0,7d008000 {
usb@7d008000 {
status = "okay";
};
usb-phy@0,7d008000 {
usb-phy@7d008000 {
status = "okay";
vbus-supply = <&vdd_usb3_vbus>;
};
......@@ -973,7 +976,7 @@ lid {
linux,input-type = <5>;
linux,code = <0>;
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
power {
......@@ -981,7 +984,7 @@ power {
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};
......
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View file @ 2ec3240f
......@@ -11,7 +11,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
pcie-controller@0,01003000 {
pcie-controller@01003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
......@@ -77,7 +77,7 @@ pci@2,0 {
};
};
host1x@0,50000000 {
host1x@50000000 {
compatible = "nvidia,tegra124-host1x", "simple-bus";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
......@@ -92,7 +92,7 @@ host1x@0,50000000 {
ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
dc@0,54200000 {
dc@54200000 {
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
......@@ -107,7 +107,7 @@ dc@0,54200000 {
nvidia,head = <0>;
};
dc@0,54240000 {
dc@54240000 {
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
......@@ -122,7 +122,7 @@ dc@0,54240000 {
nvidia,head = <1>;
};
hdmi@0,54280000 {
hdmi@54280000 {
compatible = "nvidia,tegra124-hdmi";
reg = <0x0 0x54280000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
......@@ -134,7 +134,7 @@ hdmi@0,54280000 {
status = "disabled";
};
sor@0,54540000 {
sor@54540000 {
compatible = "nvidia,tegra124-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
......@@ -148,7 +148,7 @@ sor@0,54540000 {
status = "disabled";
};
dpaux: dpaux@0,545c0000 {
dpaux: dpaux@545c0000 {
compatible = "nvidia,tegra124-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
......@@ -161,7 +161,7 @@ dpaux: dpaux@0,545c0000 {
};
};
gic: interrupt-controller@0,50041000 {
gic: interrupt-controller@50041000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
......@@ -174,7 +174,7 @@ gic: interrupt-controller@0,50041000 {
interrupt-parent = <&gic>;
};
gpu@0,57000000 {
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
......@@ -201,7 +201,7 @@ lic: interrupt-controller@60004000 {
interrupt-parent = <&gic>;
};
timer@0,60005000 {
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
......@@ -214,7 +214,7 @@ timer@0,60005000 {
clock-names = "timer";
};
tegra_car: clock@0,60006000 {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra132-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
......@@ -222,12 +222,12 @@ tegra_car: clock@0,60006000 {
nvidia,external-memory-controller = <&emc>;
};
flow-controller@0,60007000 {
flow-controller@60007000 {
compatible = "nvidia,tegra124-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};
actmon@0,6000c800 {
actmon@6000c800 {
compatible = "nvidia,tegra124-actmon";
reg = <0x0 0x6000c800 0x0 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
......@@ -238,7 +238,7 @@ actmon@0,6000c800 {
reset-names = "actmon";
};
gpio: gpio@0,6000d000 {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
......@@ -255,7 +255,7 @@ gpio: gpio@0,6000d000 {
interrupt-controller;
};
apbdma: dma@0,60020000 {
apbdma: dma@60020000 {
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
reg = <0x0 0x60020000 0x0 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -297,13 +297,13 @@ apbdma: dma@0,60020000 {
#dma-cells = <1>;
};
apbmisc@0,70000800 {
apbmisc@70000800 {
compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
};
pinmux: pinmux@0,70000868 {
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra124-pinmux";
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
......@@ -315,10 +315,10 @@ pinmux: pinmux@0,70000868 {
* driver and APB DMA based serial driver for higher baudrate
* and performance. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* the APB DMA based serial driver, the compatible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@0,70006000 {
uarta: serial@70006000 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
......@@ -332,7 +332,7 @@ uarta: serial@0,70006000 {
status = "disabled";
};
uartb: serial@0,70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
......@@ -346,7 +346,7 @@ uartb: serial@0,70006040 {
status = "disabled";
};
uartc: serial@0,70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
......@@ -360,7 +360,7 @@ uartc: serial@0,70006200 {
status = "disabled";
};
uartd: serial@0,70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
......@@ -374,7 +374,7 @@ uartd: serial@0,70006300 {
status = "disabled";
};
pwm: pwm@0,7000a000 {
pwm: pwm@7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
......@@ -385,7 +385,7 @@ pwm: pwm@0,7000a000 {
status = "disabled";
};
i2c@0,7000c000 {
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
......@@ -400,7 +400,7 @@ i2c@0,7000c000 {
status = "disabled";
};
i2c@0,7000c400 {
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
......@@ -415,7 +415,7 @@ i2c@0,7000c400 {
status = "disabled";
};
i2c@0,7000c500 {
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -430,7 +430,7 @@ i2c@0,7000c500 {
status = "disabled";
};
i2c@0,7000c700 {
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
......@@ -445,7 +445,7 @@ i2c@0,7000c700 {
status = "disabled";
};
i2c@0,7000d000 {
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
......@@ -460,7 +460,7 @@ i2c@0,7000d000 {
status = "disabled";
};
i2c@0,7000d100 {
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
......@@ -475,7 +475,7 @@ i2c@0,7000d100 {
status = "disabled";
};
spi@0,7000d400 {
spi@7000d400 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
......@@ -490,7 +490,7 @@ spi@0,7000d400 {
status = "disabled";
};
spi@0,7000d600 {
spi@7000d600 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
......@@ -505,7 +505,7 @@ spi@0,7000d600 {
status = "disabled";
};
spi@0,7000d800 {
spi@7000d800 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
......@@ -520,7 +520,7 @@ spi@0,7000d800 {
status = "disabled";
};
spi@0,7000da00 {
spi@7000da00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
......@@ -535,7 +535,7 @@ spi@0,7000da00 {
status = "disabled";
};
spi@0,7000dc00 {
spi@7000dc00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000dc00 0x0 0x200>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
......@@ -550,7 +550,7 @@ spi@0,7000dc00 {
status = "disabled";
};
spi@0,7000de00 {
spi@7000de00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000de00 0x0 0x200>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
......@@ -565,7 +565,7 @@ spi@0,7000de00 {
status = "disabled";
};
rtc@0,7000e000 {
rtc@7000e000 {
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -573,14 +573,14 @@ rtc@0,7000e000 {
clock-names = "rtc";
};
pmc@0,7000e400 {
pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
fuse@0,7000f800 {
fuse@7000f800 {
compatible = "nvidia,tegra124-efuse";
reg = <0x0 0x7000f800 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_FUSE>;
......@@ -589,7 +589,7 @@ fuse@0,7000f800 {
reset-names = "fuse";
};
mc: memory-controller@0,70019000 {
mc: memory-controller@70019000 {
compatible = "nvidia,tegra132-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
......@@ -600,14 +600,14 @@ mc: memory-controller@0,70019000 {
#iommu-cells = <1>;
};
emc: emc@0,7001b000 {
emc: emc@7001b000 {
compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
nvidia,memory-controller = <&mc>;
};
sata@0,70020000 {
sata@70020000 {
compatible = "nvidia,tegra124-ahci";
reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
<0x0 0x70020000 0x0 0x7000>; /* SATA */
......@@ -626,7 +626,7 @@ sata@0,70020000 {
status = "disabled";
};
hda@0,70030000 {
hda@70030000 {
compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
"nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
......@@ -642,7 +642,7 @@ hda@0,70030000 {
status = "disabled";
};
padctl: padctl@0,7009f000 {
padctl: padctl@7009f000 {
compatible = "nvidia,tegra132-xusb-padctl",
"nvidia,tegra124-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
......@@ -682,7 +682,7 @@ utmi-2 {
};
};
sdhci@0,700b0000 {
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
......@@ -693,7 +693,7 @@ sdhci@0,700b0000 {
status = "disabled";
};
sdhci@0,700b0200 {
sdhci@700b0200 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
......@@ -704,7 +704,7 @@ sdhci@0,700b0200 {
status = "disabled";
};
sdhci@0,700b0400 {
sdhci@700b0400 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
......@@ -715,7 +715,7 @@ sdhci@0,700b0400 {
status = "disabled";
};
sdhci@0,700b0600 {
sdhci@700b0600 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
......@@ -726,7 +726,7 @@ sdhci@0,700b0600 {
status = "disabled";
};
soctherm: thermal-sensor@0,700e2000 {
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x0 0x700e2000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
......@@ -738,7 +738,7 @@ soctherm: thermal-sensor@0,700e2000 {
#thermal-sensor-cells = <1>;
};
ahub@0,70300000 {
ahub@70300000 {
compatible = "nvidia,tegra124-ahub";
reg = <0x0 0x70300000 0x0 0x200>,
<0x0 0x70300800 0x0 0x800>,
......@@ -790,7 +790,7 @@ ahub@0,70300000 {
#address-cells = <2>;
#size-cells = <2>;
tegra_i2s0: i2s@0,70301000 {
tegra_i2s0: i2s@70301000 {
compatible = "nvidia,tegra124-i2s";
reg = <0x0 0x70301000 0x0 0x100>;
nvidia,ahub-cif-ids = <4 4>;
......@@ -801,7 +801,7 @@ tegra_i2s0: i2s@0,70301000 {
status = "disabled";
};
tegra_i2s1: i2s@0,70301100 {
tegra_i2s1: i2s@70301100 {
compatible = "nvidia,tegra124-i2s";
reg = <0x0 0x70301100 0x0 0x100>;
nvidia,ahub-cif-ids = <5 5>;
......@@ -812,7 +812,7 @@ tegra_i2s1: i2s@0,70301100 {
status = "disabled";
};
tegra_i2s2: i2s@0,70301200 {
tegra_i2s2: i2s@70301200 {
compatible = "nvidia,tegra124-i2s";
reg = <0x0 0x70301200 0x0 0x100>;
nvidia,ahub-cif-ids = <6 6>;
......@@ -823,7 +823,7 @@ tegra_i2s2: i2s@0,70301200 {
status = "disabled";
};
tegra_i2s3: i2s@0,70301300 {
tegra_i2s3: i2s@70301300 {
compatible = "nvidia,tegra124-i2s";
reg = <0x0 0x70301300 0x0 0x100>;
nvidia,ahub-cif-ids = <7 7>;
......@@ -834,7 +834,7 @@ tegra_i2s3: i2s@0,70301300 {
status = "disabled";
};
tegra_i2s4: i2s@0,70301400 {
tegra_i2s4: i2s@70301400 {
compatible = "nvidia,tegra124-i2s";
reg = <0x0 0x70301400 0x0 0x100>;
nvidia,ahub-cif-ids = <8 8>;
......@@ -846,7 +846,7 @@ tegra_i2s4: i2s@0,70301400 {
};
};
usb@0,7d000000 {
usb@7d000000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
......@@ -859,7 +859,7 @@ usb@0,7d000000 {
status = "disabled";
};
phy1: usb-phy@0,7d000000 {
phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
......@@ -884,7 +884,7 @@ phy1: usb-phy@0,7d000000 {
status = "disabled";
};
usb@0,7d004000 {
usb@7d004000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
......@@ -897,7 +897,7 @@ usb@0,7d004000 {
status = "disabled";
};
phy2: usb-phy@0,7d004000 {
phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
......@@ -921,7 +921,7 @@ phy2: usb-phy@0,7d004000 {
status = "disabled";
};
usb@0,7d008000 {
usb@7d008000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d008000 0x0 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
......@@ -934,7 +934,7 @@ usb@0,7d008000 {
status = "disabled";
};
phy3: usb-phy@0,7d008000 {
phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d008000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
......
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View file @ 2ec3240f
......@@ -5,7 +5,7 @@ / {
compatible = "nvidia,p2180", "nvidia,tegra210";
aliases {
rtc1 = "/rtc@0,7000e000";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
......@@ -15,16 +15,16 @@ memory {
};
/* debug port */
serial@0,70006000 {
serial@70006000 {
status = "okay";
};
pmc@0,7000e400 {
pmc@7000e400 {
nvidia,invert-interrupt;
};
/* eMMC */
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
......
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
View file @ 2ec3240f
......@@ -5,31 +5,35 @@ / {
compatible = "nvidia,p2530", "nvidia,tegra210";
aliases {
rtc1 = "/rtc@0,7000e000";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
/* debug port */
serial@0,70006000 {
serial@70006000 {
status = "okay";
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
pmc@0,7000e400 {
pmc@7000e400 {
nvidia,invert-interrupt;
};
/* eMMC */
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
......
arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
View file @ 2ec3240f
......@@ -7,7 +7,7 @@ / {
model = "NVIDIA Tegra210 P2571 reference design";
compatible = "nvidia,p2571", "nvidia,tegra210";
pinmux: pinmux@0,700008d4 {
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
......
arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi
View file @ 2ec3240f
......@@ -2,7 +2,7 @@ / {
model = "NVIDIA Tegra210 P2595 I/O board";
compatible = "nvidia,p2595", "nvidia,tegra210";
pinmux: pinmux@0,700008d4 {
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
......
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View file @ 2ec3240f
#include <dt-bindings/input/input.h>
/ {
model = "NVIDIA Tegra210 P2597 I/O board";
compatible = "nvidia,p2597", "nvidia,tegra210";
pinmux: pinmux@0,700008d4 {
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
......@@ -1260,11 +1262,35 @@ shutdown {
};
/* MMC/SD */
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
};
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
volume_down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
volume_up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
};
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts 0 → 100644
View file @ 2ec3240f
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210.dtsi"
/ {
model = "Google Pixel C";
compatible = "google,smaug-rev8", "google,smaug-rev7",
"google,smaug-rev6", "google,smaug-rev5",
"google,smaug-rev4", "google,smaug-rev3",
"google,smaug-rev1", "google,smaug", "nvidia,tegra210";
aliases {
serial0 = &uarta;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
state_boot: pinmux {
pex_l0_rst_n_pa0 {
nvidia,pins = "pex_l0_rst_n_pa0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
pex_l0_clkreq_n_pa1 {
nvidia,pins = "pex_l0_clkreq_n_pa1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
pex_wake_n_pa2 {
nvidia,pins = "pex_wake_n_pa2";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
pex_l1_rst_n_pa3 {
nvidia,pins = "pex_l1_rst_n_pa3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
pex_l1_clkreq_n_pa4 {
nvidia,pins = "pex_l1_clkreq_n_pa4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
sata_led_active_pa5 {
nvidia,pins = "sata_led_active_pa5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pa6 {
nvidia,pins = "pa6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap1_fs_pb0 {
nvidia,pins = "dap1_fs_pb0";
nvidia,function = "i2s1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap1_din_pb1 {
nvidia,pins = "dap1_din_pb1";
nvidia,function = "i2s1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap1_dout_pb2 {
nvidia,pins = "dap1_dout_pb2";
nvidia,function = "i2s1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap1_sclk_pb3 {
nvidia,pins = "dap1_sclk_pb3";
nvidia,function = "i2s1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi2_mosi_pb4 {
nvidia,pins = "spi2_mosi_pb4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi2_miso_pb5 {
nvidia,pins = "spi2_miso_pb5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi2_sck_pb6 {
nvidia,pins = "spi2_sck_pb6";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi2_cs0_pb7 {
nvidia,pins = "spi2_cs0_pb7";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi1_mosi_pc0 {
nvidia,pins = "spi1_mosi_pc0";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi1_miso_pc1 {
nvidia,pins = "spi1_miso_pc1";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi1_sck_pc2 {
nvidia,pins = "spi1_sck_pc2";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi1_cs0_pc3 {
nvidia,pins = "spi1_cs0_pc3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi1_cs1_pc4 {
nvidia,pins = "spi1_cs1_pc4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi4_sck_pc5 {
nvidia,pins = "spi4_sck_pc5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi4_cs0_pc6 {
nvidia,pins = "spi4_cs0_pc6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi4_mosi_pc7 {
nvidia,pins = "spi4_mosi_pc7";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spi4_miso_pd0 {
nvidia,pins = "spi4_miso_pd0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart3_tx_pd1 {
nvidia,pins = "uart3_tx_pd1";
nvidia,function = "uartc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart3_rx_pd2 {
nvidia,pins = "uart3_rx_pd2";
nvidia,function = "uartc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart3_rts_pd3 {
nvidia,pins = "uart3_rts_pd3";
nvidia,function = "uartc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart3_cts_pd4 {
nvidia,pins = "uart3_cts_pd4";
nvidia,function = "uartc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic1_clk_pe0 {
nvidia,pins = "dmic1_clk_pe0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic1_dat_pe1 {
nvidia,pins = "dmic1_dat_pe1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic2_clk_pe2 {
nvidia,pins = "dmic2_clk_pe2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic2_dat_pe3 {
nvidia,pins = "dmic2_dat_pe3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic3_clk_pe4 {
nvidia,pins = "dmic3_clk_pe4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dmic3_dat_pe5 {
nvidia,pins = "dmic3_dat_pe5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pe6 {
nvidia,pins = "pe6";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pe7 {
nvidia,pins = "pe7";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gen3_i2c_scl_pf0 {
nvidia,pins = "gen3_i2c_scl_pf0";
nvidia,function = "i2c3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
gen3_i2c_sda_pf1 {
nvidia,pins = "gen3_i2c_sda_pf1";
nvidia,function = "i2c3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
uart2_tx_pg0 {
nvidia,pins = "uart2_tx_pg0";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart2_rx_pg1 {
nvidia,pins = "uart2_rx_pg1";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart2_rts_pg2 {
nvidia,pins = "uart2_rts_pg2";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart2_cts_pg3 {
nvidia,pins = "uart2_cts_pg3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
wifi_en_ph0 {
nvidia,pins = "wifi_en_ph0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
wifi_rst_ph1 {
nvidia,pins = "wifi_rst_ph1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
wifi_wake_ap_ph2 {
nvidia,pins = "wifi_wake_ap_ph2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ap_wake_bt_ph3 {
nvidia,pins = "ap_wake_bt_ph3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
bt_rst_ph4 {
nvidia,pins = "bt_rst_ph4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
bt_wake_ap_ph5 {
nvidia,pins = "bt_wake_ap_ph5";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ph6 {
nvidia,pins = "ph6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ap_wake_nfc_ph7 {
nvidia,pins = "ap_wake_nfc_ph7";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
nfc_en_pi0 {
nvidia,pins = "nfc_en_pi0";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
nfc_int_pi1 {
nvidia,pins = "nfc_int_pi1";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gps_en_pi2 {
nvidia,pins = "gps_en_pi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gps_rst_pi3 {
nvidia,pins = "gps_rst_pi3";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart4_tx_pi4 {
nvidia,pins = "uart4_tx_pi4";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart4_rx_pi5 {
nvidia,pins = "uart4_rx_pi5";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart4_rts_pi6 {
nvidia,pins = "uart4_rts_pi6";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart4_cts_pi7 {
nvidia,pins = "uart4_cts_pi7";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gen1_i2c_sda_pj0 {
nvidia,pins = "gen1_i2c_sda_pj0";
nvidia,function = "i2c1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
gen1_i2c_scl_pj1 {
nvidia,pins = "gen1_i2c_scl_pj1";
nvidia,function = "i2c1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
gen2_i2c_scl_pj2 {
nvidia,pins = "gen2_i2c_scl_pj2";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
};
gen2_i2c_sda_pj3 {
nvidia,pins = "gen2_i2c_sda_pj3";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
};
dap4_fs_pj4 {
nvidia,pins = "dap4_fs_pj4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap4_din_pj5 {
nvidia,pins = "dap4_din_pj5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap4_dout_pj6 {
nvidia,pins = "dap4_dout_pj6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap4_sclk_pj7 {
nvidia,pins = "dap4_sclk_pj7";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk0 {
nvidia,pins = "pk0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk1 {
nvidia,pins = "pk1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk2 {
nvidia,pins = "pk2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk3 {
nvidia,pins = "pk3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk4 {
nvidia,pins = "pk4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk5 {
nvidia,pins = "pk5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk6 {
nvidia,pins = "pk6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pk7 {
nvidia,pins = "pk7";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pl0 {
nvidia,pins = "pl0";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pl1 {
nvidia,pins = "pl1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_clk_pm0 {
nvidia,pins = "sdmmc1_clk_pm0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_cmd_pm1 {
nvidia,pins = "sdmmc1_cmd_pm1";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_dat3_pm2 {
nvidia,pins = "sdmmc1_dat3_pm2";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_dat2_pm3 {
nvidia,pins = "sdmmc1_dat2_pm3";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_dat1_pm4 {
nvidia,pins = "sdmmc1_dat1_pm4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc1_dat0_pm5 {
nvidia,pins = "sdmmc1_dat0_pm5";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_clk_pp0 {
nvidia,pins = "sdmmc3_clk_pp0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_cmd_pp1 {
nvidia,pins = "sdmmc3_cmd_pp1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat3_pp2 {
nvidia,pins = "sdmmc3_dat3_pp2";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat2_pp3 {
nvidia,pins = "sdmmc3_dat2_pp3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat1_pp4 {
nvidia,pins = "sdmmc3_dat1_pp4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat0_pp5 {
nvidia,pins = "sdmmc3_dat0_pp5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam1_mclk_ps0 {
nvidia,pins = "cam1_mclk_ps0";
nvidia,function = "extperiph3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam2_mclk_ps1 {
nvidia,pins = "cam2_mclk_ps1";
nvidia,function = "extperiph3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam_i2c_scl_ps2 {
nvidia,pins = "cam_i2c_scl_ps2";
nvidia,function = "i2cvi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
cam_i2c_sda_ps3 {
nvidia,pins = "cam_i2c_sda_ps3";
nvidia,function = "i2cvi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
cam_rst_ps4 {
nvidia,pins = "cam_rst_ps4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam_af_en_ps5 {
nvidia,pins = "cam_af_en_ps5";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam_flash_en_ps6 {
nvidia,pins = "cam_flash_en_ps6";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam1_pwdn_ps7 {
nvidia,pins = "cam1_pwdn_ps7";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam2_pwdn_pt0 {
nvidia,pins = "cam2_pwdn_pt0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam1_strobe_pt1 {
nvidia,pins = "cam1_strobe_pt1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart1_tx_pu0 {
nvidia,pins = "uart1_tx_pu0";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart1_rx_pu1 {
nvidia,pins = "uart1_rx_pu1";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart1_rts_pu2 {
nvidia,pins = "uart1_rts_pu2";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
uart1_cts_pu3 {
nvidia,pins = "uart1_cts_pu3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_bl_pwm_pv0 {
nvidia,pins = "lcd_bl_pwm_pv0";
nvidia,function = "rsvd3";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_bl_en_pv1 {
nvidia,pins = "lcd_bl_en_pv1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_rst_pv2 {
nvidia,pins = "lcd_rst_pv2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_gpio1_pv3 {
nvidia,pins = "lcd_gpio1_pv3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_gpio2_pv4 {
nvidia,pins = "lcd_gpio2_pv4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ap_ready_pv5 {
nvidia,pins = "ap_ready_pv5";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
touch_rst_pv6 {
nvidia,pins = "touch_rst_pv6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
touch_clk_pv7 {
nvidia,pins = "touch_clk_pv7";
nvidia,function = "touch";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
modem_wake_ap_px0 {
nvidia,pins = "modem_wake_ap_px0";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
touch_int_px1 {
nvidia,pins = "touch_int_px1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
motion_int_px2 {
nvidia,pins = "motion_int_px2";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
als_prox_int_px3 {
nvidia,pins = "als_prox_int_px3";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
temp_alert_px4 {
nvidia,pins = "temp_alert_px4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
button_power_on_px5 {
nvidia,pins = "button_power_on_px5";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
button_vol_up_px6 {
nvidia,pins = "button_vol_up_px6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
button_vol_down_px7 {
nvidia,pins = "button_vol_down_px7";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
button_slide_sw_py0 {
nvidia,pins = "button_slide_sw_py0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
button_home_py1 {
nvidia,pins = "button_home_py1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
lcd_te_py2 {
nvidia,pins = "lcd_te_py2";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pwr_i2c_scl_py3 {
nvidia,pins = "pwr_i2c_scl_py3";
nvidia,function = "i2cpmu";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
pwr_i2c_sda_py4 {
nvidia,pins = "pwr_i2c_sda_py4";
nvidia,function = "i2cpmu";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
clk_32k_out_py5 {
nvidia,pins = "clk_32k_out_py5";
nvidia,function = "soc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz0 {
nvidia,pins = "pz0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz1 {
nvidia,pins = "pz1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz2 {
nvidia,pins = "pz2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz3 {
nvidia,pins = "pz3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz4 {
nvidia,pins = "pz4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pz5 {
nvidia,pins = "pz5";
nvidia,function = "soc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap2_fs_paa0 {
nvidia,pins = "dap2_fs_paa0";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap2_sclk_paa1 {
nvidia,pins = "dap2_sclk_paa1";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap2_din_paa2 {
nvidia,pins = "dap2_din_paa2";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dap2_dout_paa3 {
nvidia,pins = "dap2_dout_paa3";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
aud_mclk_pbb0 {
nvidia,pins = "aud_mclk_pbb0";
nvidia,function = "aud";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dvfs_clk_pbb2 {
nvidia,pins = "dvfs_clk_pbb2";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gpio_x1_aud_pbb3 {
nvidia,pins = "gpio_x1_aud_pbb3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gpio_x3_aud_pbb4 {
nvidia,pins = "gpio_x3_aud_pbb4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
hdmi_cec_pcc0 {
nvidia,pins = "hdmi_cec_pcc0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
hdmi_int_dp_hpd_pcc1 {
nvidia,pins = "hdmi_int_dp_hpd_pcc1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
spdif_out_pcc2 {
nvidia,pins = "spdif_out_pcc2";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
spdif_in_pcc3 {
nvidia,pins = "spdif_in_pcc3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
usb_vbus_en0_pcc4 {
nvidia,pins = "usb_vbus_en0_pcc4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
usb_vbus_en1_pcc5 {
nvidia,pins = "usb_vbus_en1_pcc5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
dp_hpd0_pcc6 {
nvidia,pins = "dp_hpd0_pcc6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pcc7 {
nvidia,pins = "pcc7";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
};
spi2_cs1_pdd0 {
nvidia,pins = "spi2_cs1_pdd0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_sck_pee0 {
nvidia,pins = "qspi_sck_pee0";
nvidia,function = "qspi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_cs_n_pee1 {
nvidia,pins = "qspi_cs_n_pee1";
nvidia,function = "qspi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_io0_pee2 {
nvidia,pins = "qspi_io0_pee2";
nvidia,function = "qspi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_io1_pee3 {
nvidia,pins = "qspi_io1_pee3";
nvidia,function = "qspi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_io2_pee4 {
nvidia,pins = "qspi_io2_pee4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
qspi_io3_pee5 {
nvidia,pins = "qspi_io3_pee5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
core_pwr_req {
nvidia,pins = "core_pwr_req";
nvidia,function = "core";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cpu_pwr_req {
nvidia,pins = "cpu_pwr_req";
nvidia,function = "cpu";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pwr_int_n {
nvidia,pins = "pwr_int_n";
nvidia,function = "pmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
clk_32k_in {
nvidia,pins = "clk_32k_in";
nvidia,function = "clk";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
jtag_rtck {
nvidia,pins = "jtag_rtck";
nvidia,function = "jtag";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
clk_req {
nvidia,pins = "clk_req";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
shutdown {
nvidia,pins = "shutdown";
nvidia,function = "shutdown";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
};
};
serial@70006000 {
status = "okay";
};
i2c@7000c400 {
status = "okay";
clock-frequency = <1000000>;
ec@1e {
compatible = "google,cros-ec-i2c";
reg = <0x1e>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
ec_i2c_0: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
#address-cells = <1>;
#size-cells = <0>;
google,remote-bus = <0>;
battery: bq27742@55 {
compatible = "ti,bq27742";
reg = <0x55>;
battery-name = "battery";
};
};
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <12000 6000>;
nvidia,core-pwr-off-time = <39053>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
status = "okay";
};
sdhci@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
cpu@0 {
enable-method = "psci";
};
cpu@1 {
enable-method = "psci";
};
cpu@2 {
enable-method = "psci";
};
cpu@3 {
enable-method = "psci";
};
};
gpio-keys {
compatible = "gpio-keys";
gpio-keys,name = "gpio-keys";
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <30>;
wakeup-source;
};
lid {
label = "Lid";
gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
};
tablet_mode {
label = "Tablet Mode";
gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_SW>;
linux,code = <SW_TABLET_MODE>;
wakeup-source;
};
volume_down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
volume_up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View file @ 2ec3240f
......@@ -10,7 +10,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
host1x@0,50000000 {
host1x@50000000 {
compatible = "nvidia,tegra210-host1x", "simple-bus";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
......@@ -25,7 +25,7 @@ host1x@0,50000000 {
ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
dpaux1: dpaux@0,54040000 {
dpaux1: dpaux@54040000 {
compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x54040000 0x0 0x00040000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
......@@ -37,19 +37,19 @@ dpaux1: dpaux@0,54040000 {
status = "disabled";
};
vi@0,54080000 {
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x0 0x54080000 0x0 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
tsec@0,54100000 {
tsec@54100000 {
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54100000 0x0 0x00040000>;
};
dc@0,54200000 {
dc@54200000 {
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
......@@ -64,7 +64,7 @@ dc@0,54200000 {
nvidia,head = <0>;
};
dc@0,54240000 {
dc@54240000 {
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
......@@ -79,7 +79,7 @@ dc@0,54240000 {
nvidia,head = <1>;
};
dsi@0,54300000 {
dsi@54300000 {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
......@@ -96,19 +96,19 @@ dsi@0,54300000 {
#size-cells = <0>;
};
vic@0,54340000 {
vic@54340000 {
compatible = "nvidia,tegra210-vic";
reg = <0x0 0x54340000 0x0 0x00040000>;
status = "disabled";
};
nvjpg@0,54380000 {
nvjpg@54380000 {
compatible = "nvidia,tegra210-nvjpg";
reg = <0x0 0x54380000 0x0 0x00040000>;
status = "disabled";
};
dsi@0,54400000 {
dsi@54400000 {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54400000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
......@@ -125,25 +125,25 @@ dsi@0,54400000 {
#size-cells = <0>;
};
nvdec@0,54480000 {
nvdec@54480000 {
compatible = "nvidia,tegra210-nvdec";
reg = <0x0 0x54480000 0x0 0x00040000>;
status = "disabled";
};
nvenc@0,544c0000 {
nvenc@544c0000 {
compatible = "nvidia,tegra210-nvenc";
reg = <0x0 0x544c0000 0x0 0x00040000>;
status = "disabled";
};
tsec@0,54500000 {
tsec@54500000 {
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54500000 0x0 0x00040000>;
status = "disabled";
};
sor@0,54540000 {
sor@54540000 {
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
......@@ -157,7 +157,7 @@ sor@0,54540000 {
status = "disabled";
};
sor@0,54580000 {
sor@54580000 {
compatible = "nvidia,tegra210-sor1";
reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
......@@ -171,7 +171,7 @@ sor@0,54580000 {
status = "disabled";
};
dpaux: dpaux@0,545c0000 {
dpaux: dpaux@545c0000 {
compatible = "nvidia,tegra124-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
......@@ -183,21 +183,21 @@ dpaux: dpaux@0,545c0000 {
status = "disabled";
};
isp@0,54600000 {
isp@54600000 {
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
isp@0,54680000 {
isp@54680000 {
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c@0,546c0000 {
i2c@546c0000 {
compatible = "nvidia,tegra210-i2c-vi";
reg = <0x0 0x546c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
......@@ -205,7 +205,7 @@ i2c@0,546c0000 {
};
};
gic: interrupt-controller@0,50041000 {
gic: interrupt-controller@50041000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
......@@ -218,7 +218,7 @@ gic: interrupt-controller@0,50041000 {
interrupt-parent = <&gic>;
};
gpu@0,57000000 {
gpu@57000000 {
compatible = "nvidia,gm20b";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
......@@ -226,14 +226,18 @@ gpu@0,57000000 {
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&tegra_car TEGRA210_CLK_GPU>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>;
clock-names = "gpu", "pwr";
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
clock-names = "gpu", "pwr", "ref";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
lic: interrupt-controller@0,60004000 {
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra210-ictlr";
reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
<0x0 0x60004100 0x0 0x40>, /* secondary controller */
......@@ -246,7 +250,7 @@ lic: interrupt-controller@0,60004000 {
interrupt-parent = <&gic>;
};
timer@0,60005000 {
timer@60005000 {
compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
......@@ -259,19 +263,19 @@ timer@0,60005000 {
clock-names = "timer";
};
tegra_car: clock@0,60006000 {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
flow-controller@0,60007000 {
flow-controller@60007000 {
compatible = "nvidia,tegra210-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};
gpio: gpio@0,6000d000 {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
......@@ -288,7 +292,7 @@ gpio: gpio@0,6000d000 {
interrupt-controller;
};
apbdma: dma@0,60020000 {
apbdma: dma@60020000 {
compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
reg = <0x0 0x60020000 0x0 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -330,13 +334,13 @@ apbdma: dma@0,60020000 {
#dma-cells = <1>;
};
apbmisc@0,70000800 {
apbmisc@70000800 {
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
};
pinmux: pinmux@0,700008d4 {
pinmux: pinmux@700008d4 {
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
......@@ -347,10 +351,10 @@ pinmux: pinmux@0,700008d4 {
* driver and APB DMA based serial driver for higher baudrate
* and performance. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* the APB DMA based serial driver, the compatible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@0,70006000 {
uarta: serial@70006000 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
......@@ -364,7 +368,7 @@ uarta: serial@0,70006000 {
status = "disabled";
};
uartb: serial@0,70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
......@@ -378,7 +382,7 @@ uartb: serial@0,70006040 {
status = "disabled";
};
uartc: serial@0,70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
......@@ -392,7 +396,7 @@ uartc: serial@0,70006200 {
status = "disabled";
};
uartd: serial@0,70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
......@@ -406,7 +410,7 @@ uartd: serial@0,70006300 {
status = "disabled";
};
pwm: pwm@0,7000a000 {
pwm: pwm@7000a000 {
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
......@@ -417,7 +421,7 @@ pwm: pwm@0,7000a000 {
status = "disabled";
};
i2c@0,7000c000 {
i2c@7000c000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
......@@ -432,7 +436,7 @@ i2c@0,7000c000 {
status = "disabled";
};
i2c@0,7000c400 {
i2c@7000c400 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
......@@ -447,7 +451,7 @@ i2c@0,7000c400 {
status = "disabled";
};
i2c@0,7000c500 {
i2c@7000c500 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -462,7 +466,7 @@ i2c@0,7000c500 {
status = "disabled";
};
i2c@0,7000c700 {
i2c@7000c700 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
......@@ -477,7 +481,7 @@ i2c@0,7000c700 {
status = "disabled";
};
i2c@0,7000d000 {
i2c@7000d000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
......@@ -492,7 +496,7 @@ i2c@0,7000d000 {
status = "disabled";
};
i2c@0,7000d100 {
i2c@7000d100 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
......@@ -507,7 +511,7 @@ i2c@0,7000d100 {
status = "disabled";
};
spi@0,7000d400 {
spi@7000d400 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
......@@ -522,7 +526,7 @@ spi@0,7000d400 {
status = "disabled";
};
spi@0,7000d600 {
spi@7000d600 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
......@@ -537,7 +541,7 @@ spi@0,7000d600 {
status = "disabled";
};
spi@0,7000d800 {
spi@7000d800 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
......@@ -552,7 +556,7 @@ spi@0,7000d800 {
status = "disabled";
};
spi@0,7000da00 {
spi@7000da00 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
......@@ -567,7 +571,7 @@ spi@0,7000da00 {
status = "disabled";
};
rtc@0,7000e000 {
rtc@7000e000 {
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -575,16 +579,14 @@ rtc@0,7000e000 {
clock-names = "rtc";
};
pmc: pmc@0,7000e400 {
pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#power-domain-cells = <1>;
};
fuse@0,7000f800 {
fuse@7000f800 {
compatible = "nvidia,tegra210-efuse";
reg = <0x0 0x7000f800 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
......@@ -593,7 +595,7 @@ fuse@0,7000f800 {
reset-names = "fuse";
};
mc: memory-controller@0,70019000 {
mc: memory-controller@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA210_CLK_MC>;
......@@ -604,7 +606,7 @@ mc: memory-controller@0,70019000 {
#iommu-cells = <1>;
};
hda@0,70030000 {
hda@70030000 {
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
......@@ -619,7 +621,7 @@ hda@0,70030000 {
status = "disabled";
};
sdhci@0,700b0000 {
sdhci@700b0000 {
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
......@@ -630,7 +632,7 @@ sdhci@0,700b0000 {
status = "disabled";
};
sdhci@0,700b0200 {
sdhci@700b0200 {
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
......@@ -641,7 +643,7 @@ sdhci@0,700b0200 {
status = "disabled";
};
sdhci@0,700b0400 {
sdhci@700b0400 {
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
......@@ -652,7 +654,7 @@ sdhci@0,700b0400 {
status = "disabled";
};
sdhci@0,700b0600 {
sdhci@700b0600 {
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
......@@ -663,7 +665,7 @@ sdhci@0,700b0600 {
status = "disabled";
};
mipi: mipi@0,700e3000 {
mipi: mipi@700e3000 {
compatible = "nvidia,tegra210-mipi";
reg = <0x0 0x700e3000 0x0 0x100>;
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
......@@ -671,7 +673,7 @@ mipi: mipi@0,700e3000 {
#nvidia,mipi-calibrate-cells = <1>;
};
spi@0,70410000 {
spi@70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
......@@ -686,7 +688,7 @@ spi@0,70410000 {
status = "disabled";
};
usb@0,7d000000 {
usb@7d000000 {
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
......@@ -699,7 +701,7 @@ usb@0,7d000000 {
status = "disabled";
};
phy1: usb-phy@0,7d000000 {
phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
......@@ -724,7 +726,7 @@ phy1: usb-phy@0,7d000000 {
status = "disabled";
};
usb@0,7d004000 {
usb@7d004000 {
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
......@@ -737,7 +739,7 @@ usb@0,7d004000 {
status = "disabled";
};
phy2: usb-phy@0,7d004000 {
phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View file @ 2ec3240f
......@@ -141,62 +141,66 @@ &extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif1_pins: scif1 {
renesas,groups = "scif1_data_a", "scif1_ctrl";
renesas,function = "scif1";
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
renesas,groups = "scif2_data_a";
renesas,function = "scif2";
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk_a";
renesas,function = "scif_clk";
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
renesas,groups = "i2c2_a";
renesas,function = "i2c2";
groups = "i2c2_a";
function = "i2c2";
};
avb_pins: avb {
renesas,groups = "avb_mdc";
renesas,function = "avb";
groups = "avb_mdc";
function = "avb";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi3_pins: sd3 {
renesas,groups = "sdhi3_data4", "sdhi3_ctrl";
renesas,function = "sdhi3";
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
};
sound_pins: sound {
renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
renesas,function = "ssi";
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
renesas,function = "audio_clk";
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
usb2_pins: usb2 {
renesas,groups = "usb2";
renesas,function = "usb2";
groups = "usb2";
function = "usb2";
};
};
......@@ -388,3 +392,16 @@ &ohci1 {
&ohci2 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
status = "okay";
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 2ec3240f
......@@ -120,7 +120,6 @@ can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
status = "disabled";
};
/* External SCIF clock - to be overridden by boards that provide it */
......@@ -130,6 +129,13 @@ scif_clk: scif {
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
......@@ -1155,5 +1161,54 @@ ohci2: usb@ee0c0000 {
power-domains = <&cpg>;
status = "disabled";
};
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a7795";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&cpg>;
status = "disabled";
};
pciec1: pcie@ee800000 {
compatible = "renesas,pcie-r8a7795";
reg = <0 0xee800000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&cpg>;
status = "disabled";
};
};
};
arch/arm64/boot/dts/rockchip/Makefile
View file @ 2ec3240f
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
View file @ 2ec3240f
......@@ -40,6 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3368.dtsi"
......@@ -105,16 +106,14 @@ emmc_pwrseq: emmc-pwrseq {
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
button@0 {
power {
wakeup-source;
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <116>;
linux,code = <KEY_POWER>;
};
};
......@@ -152,7 +151,6 @@ vcc_sys: vcc-sys-regulator {
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
......
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3368.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "GeekBox";
compatible = "geekbuying,geekbox", "rockchip,rk3368";
chosen {
stdout-path = "serial2:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: gmac-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
ir: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power {
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
blue {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
label = "geekbox:blue:led";
default-state = "on";
};
red {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
label = "geekbox:red:led";
default-state = "off";
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
non-removable;
num-slots = <1>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_flash>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
};
&gmac {
status = "okay";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
clock-output-names = "xin32k", "rk808-clkout2";
#clock-cells = <1>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu";
};
vdd_log: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_log";
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
};
vcc_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
};
vcc18_flash: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_flash";
};
vcc33_lcd: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_lcd";
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
};
vcca_18: LDO_REG4 {
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_18";
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
};
vcc18_lcd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
};
vcc_sd: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
};
vcc_lan: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_lan";
};
};
};
};
&pinctrl {
ir {
ir_int: ir-int {
rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
keys {
pwr_key: pwr-key {
rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_sleep: pmic-sleep {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
};
pmic_int: pmic-int {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>; /* CRU */
rockchip,hw-tshut-polarity = <1>; /* high */
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_otg {
status = "okay";
};
&wdt {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View file @ 2ec3240f
......@@ -42,6 +42,7 @@
/dts-v1/;
#include "rk3368.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Rockchip R88";
......@@ -65,16 +66,14 @@ emmc_pwrseq: emmc-pwrseq {
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
button@0 {
power {
wakeup-source;
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <116>;
linux,code = <KEY_POWER>;
};
};
......@@ -185,7 +184,6 @@ vdd_10: vdd-10-regulator {
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
......
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 2ec3240f
......@@ -413,7 +413,71 @@ uart4: serial@ff1c0000 {
};
thermal-zones {
#include "rk3368-thermal.dtsi"
cpu {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
trips {
gpu_alert0: gpu_alert0 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
gpu_crit: gpu_crit {
temperature = <115000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
tsadc: tsadc@ff280000 {
......@@ -555,6 +619,18 @@ uart2: serial@ff690000 {
status = "disabled";
};
mbox: mbox@ff6b0000 {
compatible = "rockchip,rk3368-mailbox";
reg = <0x0 0xff6b0000 0x0 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
};
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
......@@ -926,11 +1002,11 @@ spi2_tx: spi2-tx {
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
};
};
......
arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi → arch/arm64/boot/dts/rockchip/rk3399-evb.dts
View file @ 2ec3240f
/*
* Device Tree Source for RK3368 SoC thermal
*
* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
* Caesar Wang <wxt@rock-chips.com>
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,70 +40,85 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
/ {
model = "Rockchip RK3399 Evaluation Board";
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
"google,rk3399evb-rev2";
thermal-sensors = <&tsadc 0>;
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 0>;
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
trips {
cpu_alert0: cpu_alert0 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
gpu_thermal: gpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
thermal-sensors = <&tsadc 1>;
&pwm3 {
status = "okay";
};
trips {
gpu_alert0: gpu_alert0 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
gpu_crit: gpu_crit {
temperature = <1150000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
pmic_dvs2: pmic-dvs2 {
rockchip,pins =
<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
arch/arm64/boot/dts/rockchip/rk3399.dtsi 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
compatible = "rockchip,rk3399";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_l0>;
};
core1 {
cpu = <&cpu_l1>;
};
core2 {
cpu = <&cpu_l2>;
};
core3 {
cpu = <&cpu_l3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_b0>;
};
core1 {
cpu = <&cpu_b1>;
};
};
};
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
};
cpu_l1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
};
cpu_l2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
};
cpu_l3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
};
cpu_b0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
};
cpu_b1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
xin24m: xin24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
amba {
compatible = "arm,amba-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dmac_bus: dma-controller@ff6d0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6d0000 0x0 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC0_PERILP>;
clock-names = "apb_pclk";
};
dmac_peri: dma-controller@ff6e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6e0000 0x0 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1_PERILP>;
clock-names = "apb_pclk";
};
};
sdio0: dwmmc@fe310000 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
status = "disabled";
};
sdmmc: dwmmc@fe320000 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
status = "disabled";
};
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
};
usb_host0_ohci: usb@fe3a0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
};
usb_host1_ehci: usb@fe3c0000 {
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
status = "disabled";
};
usb_host1_ohci: usb@fe3e0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
status = "disabled";
};
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
<0x0 0xfef00000 0 0xc0000>, /* GICR */
<0x0 0xfff00000 0 0x10000>, /* GICC */
<0x0 0xfff10000 0 0x10000>, /* GICH */
<0x0 0xfff20000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: interrupt-controller@fee20000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0xfee20000 0x0 0x20000>;
};
};
uart0: serial@ff180000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff180000 0x0 0x100>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
};
uart1: serial@ff190000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff190000 0x0 0x100>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
};
uart2: serial@ff1a0000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff1a0000 0x0 0x100>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart2c_xfer>;
status = "disabled";
};
uart3: serial@ff1b0000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff1b0000 0x0 0x100>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
status = "disabled";
};
spi0: spi@ff1c0000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1c0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@ff1d0000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1d0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@ff1e0000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1e0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@ff1f0000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1f0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@ff200000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff200000 0x0 0x1000>;
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon";
reg = <0x0 0xff320000 0x0 0x1000>;
};
spi3: spi@ff350000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff350000 0x0 0x1000>;
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart4: serial@ff370000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff370000 0x0 0x100>;
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
pwm0: pwm@ff420000 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@ff420010 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@ff420020 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@ff420030 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3a_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&pmucru PLL_PPLL>;
assigned-clock-rates = <676000000>;
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x10000>;
};
watchdog@ff840000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff840000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};
spdif: spdif@ff870000 {
compatible = "rockchip,rk3399-spdif";
reg = <0x0 0xff870000 0x0 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 7>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
status = "disabled";
};
i2s0: i2s@ff880000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff880000 0x0 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
status = "disabled";
};
i2s1: i2s@ff890000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
status = "disabled";
};
i2s2: i2s@ff8a0000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff8a0000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio0@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio1: gpio1@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio2: gpio2@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio3: gpio3@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio4: gpio4@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
bias-disable;
drive-strength = <12>;
};
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
bias-pull-up;
drive-strength = <8>;
};
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
bias-pull-down;
drive-strength = <4>;
};
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
bias-pull-up;
drive-strength = <2>;
};
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
bias-pull-down;
drive-strength = <12>;
};
pcfg_pull_none_13ma: pcfg-pull-none-13ma {
bias-disable;
drive-strength = <13>;
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
<1 15 RK_FUNC_2 &pcfg_pull_none>,
<1 16 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins =
<4 2 RK_FUNC_1 &pcfg_pull_none>,
<4 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins =
<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins =
<4 17 RK_FUNC_1 &pcfg_pull_none>,
<4 16 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins =
<1 12 RK_FUNC_1 &pcfg_pull_none>,
<1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins =
<3 11 RK_FUNC_2 &pcfg_pull_none>,
<3 10 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c6 {
i2c6_xfer: i2c6-xfer {
rockchip,pins =
<2 10 RK_FUNC_2 &pcfg_pull_none>,
<2 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c7 {
i2c7_xfer: i2c7-xfer {
rockchip,pins =
<2 8 RK_FUNC_2 &pcfg_pull_none>,
<2 7 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer: i2c8-xfer {
rockchip,pins =
<1 21 RK_FUNC_1 &pcfg_pull_none>,
<1 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
<3 24 RK_FUNC_1 &pcfg_pull_none>,
<3 25 RK_FUNC_1 &pcfg_pull_none>,
<3 26 RK_FUNC_1 &pcfg_pull_none>,
<3 27 RK_FUNC_1 &pcfg_pull_none>,
<3 28 RK_FUNC_1 &pcfg_pull_none>,
<3 29 RK_FUNC_1 &pcfg_pull_none>,
<3 30 RK_FUNC_1 &pcfg_pull_none>,
<3 31 RK_FUNC_1 &pcfg_pull_none>,
<4 0 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s1 {
i2s1_2ch_bus: i2s1-2ch-bus {
rockchip,pins =
<4 3 RK_FUNC_1 &pcfg_pull_none>,
<4 4 RK_FUNC_1 &pcfg_pull_none>,
<4 5 RK_FUNC_1 &pcfg_pull_none>,
<4 6 RK_FUNC_1 &pcfg_pull_none>,
<4 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
<4 21 RK_FUNC_1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
<3 6 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins =
<3 7 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins =
<3 8 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins =
<3 5 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins =
<3 4 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins =
<1 9 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins =
<1 10 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins =
<1 7 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins =
<1 8 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi2 {
spi2_clk: spi2-clk {
rockchip,pins =
<2 11 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins =
<2 12 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins =
<2 9 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins =
<2 10 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi3 {
spi3_clk: spi3-clk {
rockchip,pins =
<1 17 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_cs0: spi3-cs0 {
rockchip,pins =
<1 18 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_rx: spi3-rx {
rockchip,pins =
<1 15 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_tx: spi3-tx {
rockchip,pins =
<1 16 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi4 {
spi4_clk: spi4-clk {
rockchip,pins =
<3 2 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_cs0: spi4-cs0 {
rockchip,pins =
<3 3 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_rx: spi4-rx {
rockchip,pins =
<3 0 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_tx: spi4-tx {
rockchip,pins =
<3 1 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi5 {
spi5_clk: spi5-clk {
rockchip,pins =
<2 22 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_cs0: spi5-cs0 {
rockchip,pins =
<2 23 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_rx: spi5-rx {
rockchip,pins =
<2 20 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_tx: spi5-tx {
rockchip,pins =
<2 21 RK_FUNC_2 &pcfg_pull_up>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
<2 16 RK_FUNC_1 &pcfg_pull_up>,
<2 17 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins =
<2 18 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins =
<2 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins =
<3 12 RK_FUNC_2 &pcfg_pull_up>,
<3 13 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2a {
uart2a_xfer: uart2a-xfer {
rockchip,pins =
<4 8 RK_FUNC_2 &pcfg_pull_up>,
<4 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2b {
uart2b_xfer: uart2b-xfer {
rockchip,pins =
<4 16 RK_FUNC_2 &pcfg_pull_up>,
<4 17 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2c {
uart2c_xfer: uart2c-xfer {
rockchip,pins =
<4 19 RK_FUNC_1 &pcfg_pull_up>,
<4 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins =
<3 14 RK_FUNC_2 &pcfg_pull_up>,
<3 15 RK_FUNC_2 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins =
<3 18 RK_FUNC_2 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins =
<3 19 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins =
<1 7 RK_FUNC_1 &pcfg_pull_up>,
<1 8 RK_FUNC_1 &pcfg_pull_none>;
};
};
uarthdcp {
uarthdcp_xfer: uarthdcp-xfer {
rockchip,pins =
<4 21 RK_FUNC_2 &pcfg_pull_up>,
<4 22 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins =
<4 18 RK_FUNC_1 &pcfg_pull_none>;
};
vop0_pwm_pin: vop0-pwm-pin {
rockchip,pins =
<4 18 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins =
<4 22 RK_FUNC_1 &pcfg_pull_none>;
};
vop1_pwm_pin: vop1-pwm-pin {
rockchip,pins =
<4 18 RK_FUNC_3 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins =
<1 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm3a {
pwm3a_pin: pwm3a-pin {
rockchip,pins =
<0 6 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm3b {
pwm3b_pin: pwm3b-pin {
rockchip,pins =
<1 14 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
};
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts
View file @ 2ec3240f
......@@ -44,6 +44,7 @@
/dts-v1/;
/include/ "uniphier-ph1-ld20.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
......
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
View file @ 2ec3240f
......@@ -106,6 +106,12 @@ cpu3: cpu@101 {
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
......
arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi 0 → 120000
View file @ 2ec3240f
../../../../arm/boot/dts/uniphier-ref-daughter.dtsi
\ No newline at end of file
include/dt-bindings/clock/rk3399-cru.h 0 → 100644
View file @ 2ec3240f
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <zhengxing@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
/* core clocks */
#define PLL_APLLL 1
#define PLL_APLLB 2
#define PLL_DPLL 3
#define PLL_CPLL 4
#define PLL_GPLL 5
#define PLL_NPLL 6
#define PLL_VPLL 7
#define ARMCLKL 8
#define ARMCLKB 9
/* sclk gates (special clocks) */
#define SCLK_I2C1 65
#define SCLK_I2C2 66
#define SCLK_I2C3 67
#define SCLK_I2C5 68
#define SCLK_I2C6 69
#define SCLK_I2C7 70
#define SCLK_SPI0 71
#define SCLK_SPI1 72
#define SCLK_SPI2 73
#define SCLK_SPI4 74
#define SCLK_SPI5 75
#define SCLK_SDMMC 76
#define SCLK_SDIO 77
#define SCLK_EMMC 78
#define SCLK_TSADC 79
#define SCLK_SARADC 80
#define SCLK_UART0 81
#define SCLK_UART1 82
#define SCLK_UART2 83
#define SCLK_UART3 84
#define SCLK_SPDIF_8CH 85
#define SCLK_I2S0_8CH 86
#define SCLK_I2S1_8CH 87
#define SCLK_I2S2_8CH 88
#define SCLK_I2S_8CH_OUT 89
#define SCLK_TIMER00 90
#define SCLK_TIMER01 91
#define SCLK_TIMER02 92
#define SCLK_TIMER03 93
#define SCLK_TIMER04 94
#define SCLK_TIMER05 95
#define SCLK_TIMER06 96
#define SCLK_TIMER07 97
#define SCLK_TIMER08 98
#define SCLK_TIMER09 99
#define SCLK_TIMER10 100
#define SCLK_TIMER11 101
#define SCLK_MACREF 102
#define SCLK_MAC_RX 103
#define SCLK_MAC_TX 104
#define SCLK_MAC 105
#define SCLK_MACREF_OUT 106
#define SCLK_VOP0_PWM 107
#define SCLK_VOP1_PWM 108
#define SCLK_RGA_CORE 109
#define SCLK_ISP0 110
#define SCLK_ISP1 111
#define SCLK_HDMI_CEC 112
#define SCLK_HDMI_SFR 113
#define SCLK_DP_CORE 114
#define SCLK_PVTM_CORE_L 115
#define SCLK_PVTM_CORE_B 116
#define SCLK_PVTM_GPU 117
#define SCLK_PVTM_DDR 118
#define SCLK_MIPIDPHY_REF 119
#define SCLK_MIPIDPHY_CFG 120
#define SCLK_HSICPHY 121
#define SCLK_USBPHY480M 122
#define SCLK_USB2PHY0_REF 123
#define SCLK_USB2PHY1_REF 124
#define SCLK_UPHY0_TCPDPHY_REF 125
#define SCLK_UPHY0_TCPDCORE 126
#define SCLK_UPHY1_TCPDPHY_REF 127
#define SCLK_UPHY1_TCPDCORE 128
#define SCLK_USB3OTG0_REF 129
#define SCLK_USB3OTG1_REF 130
#define SCLK_USB3OTG0_SUSPEND 131
#define SCLK_USB3OTG1_SUSPEND 132
#define SCLK_CRYPTO0 133
#define SCLK_CRYPTO1 134
#define SCLK_CCI_TRACE 135
#define SCLK_CS 136
#define SCLK_CIF_OUT 137
#define SCLK_PCIEPHY_REF 138
#define SCLK_PCIE_CORE 139
#define SCLK_M0_PERILP 140
#define SCLK_M0_PERILP_DEC 141
#define SCLK_CM0S 142
#define SCLK_DBG_NOC 143
#define SCLK_DBG_PD_CORE_B 144
#define SCLK_DBG_PD_CORE_L 145
#define SCLK_DFIMON0_TIMER 146
#define SCLK_DFIMON1_TIMER 147
#define SCLK_INTMEM0 148
#define SCLK_INTMEM1 149
#define SCLK_INTMEM2 150
#define SCLK_INTMEM3 151
#define SCLK_INTMEM4 152
#define SCLK_INTMEM5 153
#define SCLK_SDMMC_DRV 154
#define SCLK_SDMMC_SAMPLE 155
#define SCLK_SDIO_DRV 156
#define SCLK_SDIO_SAMPLE 157
#define SCLK_VDU_CORE 158
#define SCLK_VDU_CA 159
#define SCLK_PCIE_PM 160
#define SCLK_SPDIF_REC_DPTX 161
#define SCLK_DPHY_PLL 162
#define SCLK_DPHY_TX0_CFG 163
#define SCLK_DPHY_TX1RX1_CFG 164
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
#define DCLK_VOP0 180
#define DCLK_VOP1 181
#define DCLK_VOP0_DIV 182
#define DCLK_VOP1_DIV 183
#define DCLK_M0_PERILP 184
#define FCLK_CM0S 190
/* aclk gates */
#define ACLK_PERIHP 192
#define ACLK_PERIHP_NOC 193
#define ACLK_PERILP0 194
#define ACLK_PERILP0_NOC 195
#define ACLK_PERF_PCIE 196
#define ACLK_PCIE 197
#define ACLK_INTMEM 198
#define ACLK_TZMA 199
#define ACLK_DCF 200
#define ACLK_CCI 201
#define ACLK_CCI_NOC0 202
#define ACLK_CCI_NOC1 203
#define ACLK_CCI_GRF 204
#define ACLK_CENTER 205
#define ACLK_CENTER_MAIN_NOC 206
#define ACLK_CENTER_PERI_NOC 207
#define ACLK_GPU 208
#define ACLK_PERF_GPU 209
#define ACLK_GPU_GRF 210
#define ACLK_DMAC0_PERILP 211
#define ACLK_DMAC1_PERILP 212
#define ACLK_GMAC 213
#define ACLK_GMAC_NOC 214
#define ACLK_PERF_GMAC 215
#define ACLK_VOP0_NOC 216
#define ACLK_VOP0 217
#define ACLK_VOP1_NOC 218
#define ACLK_VOP1 219
#define ACLK_RGA 220
#define ACLK_RGA_NOC 221
#define ACLK_HDCP 222
#define ACLK_HDCP_NOC 223
#define ACLK_HDCP22 224
#define ACLK_IEP 225
#define ACLK_IEP_NOC 226
#define ACLK_VIO 227
#define ACLK_VIO_NOC 228
#define ACLK_ISP0 229
#define ACLK_ISP1 230
#define ACLK_ISP0_NOC 231
#define ACLK_ISP1_NOC 232
#define ACLK_ISP0_WRAPPER 233
#define ACLK_ISP1_WRAPPER 234
#define ACLK_VCODEC 235
#define ACLK_VCODEC_NOC 236
#define ACLK_VDU 237
#define ACLK_VDU_NOC 238
#define ACLK_PERI 239
#define ACLK_EMMC 240
#define ACLK_EMMC_CORE 241
#define ACLK_EMMC_NOC 242
#define ACLK_EMMC_GRF 243
#define ACLK_USB3 244
#define ACLK_USB3_NOC 245
#define ACLK_USB3OTG0 246
#define ACLK_USB3OTG1 247
#define ACLK_USB3_RKSOC_AXI_PERF 248
#define ACLK_USB3_GRF 249
#define ACLK_GIC 250
#define ACLK_GIC_NOC 251
#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
#define ACLK_ADB400M_PD_CORE_L 258
#define ACLK_ADB400M_PD_CORE_B 259
#define ACLK_PERF_CORE_L 260
#define ACLK_PERF_CORE_B 261
#define ACLK_GIC_PRE 262
#define ACLK_VOP0_PRE 263
#define ACLK_VOP1_PRE 264
/* pclk gates */
#define PCLK_PERIHP 320
#define PCLK_PERIHP_NOC 321
#define PCLK_PERILP0 322
#define PCLK_PERILP1 323
#define PCLK_PERILP1_NOC 324
#define PCLK_PERILP_SGRF 325
#define PCLK_PERIHP_GRF 326
#define PCLK_PCIE 327
#define PCLK_SGRF 328
#define PCLK_INTR_ARB 329
#define PCLK_CENTER_MAIN_NOC 330
#define PCLK_CIC 331
#define PCLK_COREDBG_B 332
#define PCLK_COREDBG_L 333
#define PCLK_DBG_CXCS_PD_CORE_B 334
#define PCLK_DCF 335
#define PCLK_GPIO2 336
#define PCLK_GPIO3 337
#define PCLK_GPIO4 338
#define PCLK_GRF 339
#define PCLK_HSICPHY 340
#define PCLK_I2C1 341
#define PCLK_I2C2 342
#define PCLK_I2C3 343
#define PCLK_I2C5 344
#define PCLK_I2C6 345
#define PCLK_I2C7 346
#define PCLK_SPI0 347
#define PCLK_SPI1 348
#define PCLK_SPI2 349
#define PCLK_SPI4 350
#define PCLK_SPI5 351
#define PCLK_UART0 352
#define PCLK_UART1 353
#define PCLK_UART2 354
#define PCLK_UART3 355
#define PCLK_TSADC 356
#define PCLK_SARADC 357
#define PCLK_GMAC 358
#define PCLK_GMAC_NOC 359
#define PCLK_TIMER0 360
#define PCLK_TIMER1 361
#define PCLK_EDP 362
#define PCLK_EDP_NOC 363
#define PCLK_EDP_CTRL 364
#define PCLK_VIO 365
#define PCLK_VIO_NOC 366
#define PCLK_VIO_GRF 367
#define PCLK_MIPI_DSI0 368
#define PCLK_MIPI_DSI1 369
#define PCLK_HDCP 370
#define PCLK_HDCP_NOC 371
#define PCLK_HDMI_CTRL 372
#define PCLK_DP_CTRL 373
#define PCLK_HDCP22 374
#define PCLK_GASKET 375
#define PCLK_DDR 376
#define PCLK_DDR_MON 377
#define PCLK_DDR_SGRF 378
#define PCLK_ISP1_WRAPPER 379
#define PCLK_WDT 380
#define PCLK_EFUSE1024NS 381
#define PCLK_EFUSE1024S 382
#define PCLK_PMU_INTR_ARB 383
#define PCLK_MAILBOX0 384
#define PCLK_USBPHY_MUX_G 385
#define PCLK_UPHY0_TCPHY_G 386
#define PCLK_UPHY0_TCPD_G 387
#define PCLK_UPHY1_TCPHY_G 388
#define PCLK_UPHY1_TCPD_G 389
#define PCLK_ALIVE 390
/* hclk gates */
#define HCLK_PERIHP 448
#define HCLK_PERILP0 449
#define HCLK_PERILP1 450
#define HCLK_PERILP0_NOC 451
#define HCLK_PERILP1_NOC 452
#define HCLK_M0_PERILP 453
#define HCLK_M0_PERILP_NOC 454
#define HCLK_AHB1TOM 455
#define HCLK_HOST0 456
#define HCLK_HOST0_ARB 457
#define HCLK_HOST1 458
#define HCLK_HOST1_ARB 459
#define HCLK_HSIC 460
#define HCLK_SD 461
#define HCLK_SDMMC 462
#define HCLK_SDMMC_NOC 463
#define HCLK_M_CRYPTO0 464
#define HCLK_M_CRYPTO1 465
#define HCLK_S_CRYPTO0 466
#define HCLK_S_CRYPTO1 467
#define HCLK_I2S0_8CH 468
#define HCLK_I2S1_8CH 469
#define HCLK_I2S2_8CH 470
#define HCLK_SPDIF 471
#define HCLK_VOP0_NOC 472
#define HCLK_VOP0 473
#define HCLK_VOP1_NOC 474
#define HCLK_VOP1 475
#define HCLK_ROM 476
#define HCLK_IEP 477
#define HCLK_IEP_NOC 478
#define HCLK_ISP0 479
#define HCLK_ISP1 480
#define HCLK_ISP0_NOC 481
#define HCLK_ISP1_NOC 482
#define HCLK_ISP0_WRAPPER 483
#define HCLK_ISP1_WRAPPER 484
#define HCLK_RGA 485
#define HCLK_RGA_NOC 486
#define HCLK_HDCP 487
#define HCLK_HDCP_NOC 488
#define HCLK_HDCP22 489
#define HCLK_VCODEC 490
#define HCLK_VCODEC_NOC 491
#define HCLK_VDU 492
#define HCLK_VDU_NOC 493
#define HCLK_SDIO 494
#define HCLK_SDIO_NOC 495
#define HCLK_SDIOAUDIO_NOC 496
#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
/* pmu-clocks indices */
#define PLL_PPLL 1
#define SCLK_32K_SUSPEND_PMU 2
#define SCLK_SPI3_PMU 3
#define SCLK_TIMER12_PMU 4
#define SCLK_TIMER13_PMU 5
#define SCLK_UART4_PMU 6
#define SCLK_PVTM_PMU 7
#define SCLK_WIFI_PMU 8
#define SCLK_I2C0_PMU 9
#define SCLK_I2C4_PMU 10
#define SCLK_I2C8_PMU 11
#define PCLK_SRC_PMU 19
#define PCLK_PMU 20
#define PCLK_PMUGRF_PMU 21
#define PCLK_INTMEM1_PMU 22
#define PCLK_GPIO0_PMU 23
#define PCLK_GPIO1_PMU 24
#define PCLK_SGRF_PMU 25
#define PCLK_NOC_PMU 26
#define PCLK_I2C0_PMU 27
#define PCLK_I2C4_PMU 28
#define PCLK_I2C8_PMU 29
#define PCLK_RKPWM_PMU 30
#define PCLK_SPI3_PMU 31
#define PCLK_TIMER_PMU 32
#define PCLK_MAILBOX_PMU 33
#define PCLK_UART4_PMU 34
#define PCLK_WDT_M0_PMU 35
#define FCLK_CM0S_SRC_PMU 44
#define FCLK_CM0S_PMU 45
#define SCLK_CM0S_PMU 46
#define HCLK_CM0S_PMU 47
#define DCLK_CM0S_PMU 48
#define PCLK_INTR_ARB_PMU 49
#define HCLK_NOC_PMU 50
#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
/* soft-reset indices */
/* cru_softrst_con0 */
#define SRST_CORE_L0 0
#define SRST_CORE_B0 1
#define SRST_CORE_PO_L0 2
#define SRST_CORE_PO_B0 3
#define SRST_L2_L 4
#define SRST_L2_B 5
#define SRST_ADB_L 6
#define SRST_ADB_B 7
#define SRST_A_CCI 8
#define SRST_A_CCIM0_NOC 9
#define SRST_A_CCIM1_NOC 10
#define SRST_DBG_NOC 11
/* cru_softrst_con1 */
#define SRST_CORE_L0_T 16
#define SRST_CORE_L1 17
#define SRST_CORE_L2 18
#define SRST_CORE_L3 19
#define SRST_CORE_PO_L0_T 20
#define SRST_CORE_PO_L1 21
#define SRST_CORE_PO_L2 22
#define SRST_CORE_PO_L3 23
#define SRST_A_ADB400_GIC2COREL 24
#define SRST_A_ADB400_COREL2GIC 25
#define SRST_P_DBG_L 26
#define SRST_L2_L_T 28
#define SRST_ADB_L_T 29
#define SRST_A_RKPERF_L 30
#define SRST_PVTM_CORE_L 31
/* cru_softrst_con2 */
#define SRST_CORE_B0_T 32
#define SRST_CORE_B1 33
#define SRST_CORE_PO_B0_T 36
#define SRST_CORE_PO_B1 37
#define SRST_A_ADB400_GIC2COREB 40
#define SRST_A_ADB400_COREB2GIC 41
#define SRST_P_DBG_B 42
#define SRST_L2_B_T 43
#define SRST_ADB_B_T 45
#define SRST_A_RKPERF_B 46
#define SRST_PVTM_CORE_B 47
/* cru_softrst_con3 */
#define SRST_A_CCI_T 50
#define SRST_A_CCIM0_NOC_T 51
#define SRST_A_CCIM1_NOC_T 52
#define SRST_A_ADB400M_PD_CORE_B_T 53
#define SRST_A_ADB400M_PD_CORE_L_T 54
#define SRST_DBG_NOC_T 55
#define SRST_DBG_CXCS 56
#define SRST_CCI_TRACE 57
#define SRST_P_CCI_GRF 58
/* cru_softrst_con4 */
#define SRST_A_CENTER_MAIN_NOC 64
#define SRST_A_CENTER_PERI_NOC 65
#define SRST_P_CENTER_MAIN 66
#define SRST_P_DDRMON 67
#define SRST_P_CIC 68
#define SRST_P_CENTER_SGRF 69
#define SRST_DDR0_MSCH 70
#define SRST_DDRCFG0_MSCH 71
#define SRST_DDR0 72
#define SRST_DDRPHY0 73
#define SRST_DDR1_MSCH 74
#define SRST_DDRCFG1_MSCH 75
#define SRST_DDR1 76
#define SRST_DDRPHY1 77
#define SRST_DDR_CIC 78
#define SRST_PVTM_DDR 79
/* cru_softrst_con5 */
#define SRST_A_VCODEC_NOC 80
#define SRST_A_VCODEC 81
#define SRST_H_VCODEC_NOC 82
#define SRST_H_VCODEC 83
#define SRST_A_VDU_NOC 88
#define SRST_A_VDU 89
#define SRST_H_VDU_NOC 90
#define SRST_H_VDU 91
#define SRST_VDU_CORE 92
#define SRST_VDU_CA 93
/* cru_softrst_con6 */
#define SRST_A_IEP_NOC 96
#define SRST_A_VOP_IEP 97
#define SRST_A_IEP 98
#define SRST_H_IEP_NOC 99
#define SRST_H_IEP 100
#define SRST_A_RGA_NOC 102
#define SRST_A_RGA 103
#define SRST_H_RGA_NOC 104
#define SRST_H_RGA 105
#define SRST_RGA_CORE 106
#define SRST_EMMC_NOC 108
#define SRST_EMMC 109
#define SRST_EMMC_GRF 110
/* cru_softrst_con7 */
#define SRST_A_PERIHP_NOC 112
#define SRST_P_PERIHP_GRF 113
#define SRST_H_PERIHP_NOC 114
#define SRST_USBHOST0 115
#define SRST_HOSTC0_AUX 116
#define SRST_HOST0_ARB 117
#define SRST_USBHOST1 118
#define SRST_HOSTC1_AUX 119
#define SRST_HOST1_ARB 120
#define SRST_SDIO0 121
#define SRST_SDMMC 122
#define SRST_HSIC 123
#define SRST_HSIC_AUX 124
#define SRST_AHB1TOM 125
#define SRST_P_PERIHP_NOC 126
#define SRST_HSICPHY 127
/* cru_softrst_con8 */
#define SRST_A_PCIE 128
#define SRST_P_PCIE 129
#define SRST_PCIE_CORE 130
#define SRST_PCIE_MGMT 131
#define SRST_PCIE_MGMT_STICKY 132
#define SRST_PCIE_PIPE 133
#define SRST_PCIE_PM 134
#define SRST_PCIEPHY 135
#define SRST_A_GMAC_NOC 136
#define SRST_A_GMAC 137
#define SRST_P_GMAC_NOC 138
#define SRST_P_GMAC_GRF 140
#define SRST_HSICPHY_POR 142
#define SRST_HSICPHY_UTMI 143
/* cru_softrst_con9 */
#define SRST_USB2PHY0_POR 144
#define SRST_USB2PHY0_UTMI_PORT0 145
#define SRST_USB2PHY0_UTMI_PORT1 146
#define SRST_USB2PHY0_EHCIPHY 147
#define SRST_UPHY0_PIPE_L00 148
#define SRST_UPHY0 149
#define SRST_UPHY0_TCPDPWRUP 150
#define SRST_USB2PHY1_POR 152
#define SRST_USB2PHY1_UTMI_PORT0 153
#define SRST_USB2PHY1_UTMI_PORT1 154
#define SRST_USB2PHY1_EHCIPHY 155
#define SRST_UPHY1_PIPE_L00 156
#define SRST_UPHY1 157
#define SRST_UPHY1_TCPDPWRUP 158
/* cru_softrst_con10 */
#define SRST_A_PERILP0_NOC 160
#define SRST_A_DCF 161
#define SRST_GIC500 162
#define SRST_DMAC0_PERILP0 163
#define SRST_DMAC1_PERILP0 164
#define SRST_TZMA 165
#define SRST_INTMEM 166
#define SRST_ADB400_MST0 167
#define SRST_ADB400_MST1 168
#define SRST_ADB400_SLV0 169
#define SRST_ADB400_SLV1 170
#define SRST_H_PERILP0 171
#define SRST_H_PERILP0_NOC 172
#define SRST_ROM 173
#define SRST_CRYPTO_S 174
#define SRST_CRYPTO_M 175
/* cru_softrst_con11 */
#define SRST_P_DCF 176
#define SRST_CM0S_NOC 177
#define SRST_CM0S 178
#define SRST_CM0S_DBG 179
#define SRST_CM0S_PO 180
#define SRST_CRYPTO 181
#define SRST_P_PERILP1_SGRF 182
#define SRST_P_PERILP1_GRF 183
#define SRST_CRYPTO1_S 184
#define SRST_CRYPTO1_M 185
#define SRST_CRYPTO1 186
#define SRST_GIC_NOC 188
#define SRST_SD_NOC 189
#define SRST_SDIOAUDIO_BRG 190
/* cru_softrst_con12 */
#define SRST_H_PERILP1 192
#define SRST_H_PERILP1_NOC 193
#define SRST_H_I2S0_8CH 194
#define SRST_H_I2S1_8CH 195
#define SRST_H_I2S2_8CH 196
#define SRST_H_SPDIF_8CH 197
#define SRST_P_PERILP1_NOC 198
#define SRST_P_EFUSE_1024 199
#define SRST_P_EFUSE_1024S 200
#define SRST_P_I2C0 201
#define SRST_P_I2C1 202
#define SRST_P_I2C2 203
#define SRST_P_I2C3 204
#define SRST_P_I2C4 205
#define SRST_P_I2C5 206
#define SRST_P_MAILBOX0 207
/* cru_softrst_con13 */
#define SRST_P_UART0 208
#define SRST_P_UART1 209
#define SRST_P_UART2 210
#define SRST_P_UART3 211
#define SRST_P_SARADC 212
#define SRST_P_TSADC 213
#define SRST_P_SPI0 214
#define SRST_P_SPI1 215
#define SRST_P_SPI2 216
#define SRST_P_SPI3 217
#define SRST_P_SPI4 218
#define SRST_SPI0 219
#define SRST_SPI1 220
#define SRST_SPI2 221
#define SRST_SPI3 222
#define SRST_SPI4 223
/* cru_softrst_con14 */
#define SRST_I2S0_8CH 224
#define SRST_I2S1_8CH 225
#define SRST_I2S2_8CH 226
#define SRST_SPDIF_8CH 227
#define SRST_UART0 228
#define SRST_UART1 229
#define SRST_UART2 230
#define SRST_UART3 231
#define SRST_TSADC 232
#define SRST_I2C0 233
#define SRST_I2C1 234
#define SRST_I2C2 235
#define SRST_I2C3 236
#define SRST_I2C4 237
#define SRST_I2C5 238
#define SRST_SDIOAUDIO_NOC 239
/* cru_softrst_con15 */
#define SRST_A_VIO_NOC 240
#define SRST_A_HDCP_NOC 241
#define SRST_A_HDCP 242
#define SRST_H_HDCP_NOC 243
#define SRST_H_HDCP 244
#define SRST_P_HDCP_NOC 245
#define SRST_P_HDCP 246
#define SRST_P_HDMI_CTRL 247
#define SRST_P_DP_CTRL 248
#define SRST_S_DP_CTRL 249
#define SRST_C_DP_CTRL 250
#define SRST_P_MIPI_DSI0 251
#define SRST_P_MIPI_DSI1 252
#define SRST_DP_CORE 253
#define SRST_DP_I2S 254
/* cru_softrst_con16 */
#define SRST_GASKET 256
#define SRST_VIO_GRF 258
#define SRST_DPTX_SPDIF_REC 259
#define SRST_HDMI_CTRL 260
#define SRST_HDCP_CTRL 261
#define SRST_A_ISP0_NOC 262
#define SRST_A_ISP1_NOC 263
#define SRST_H_ISP0_NOC 266
#define SRST_H_ISP1_NOC 267
#define SRST_H_ISP0 268
#define SRST_H_ISP1 269
#define SRST_ISP0 270
#define SRST_ISP1 271
/* cru_softrst_con17 */
#define SRST_A_VOP0_NOC 272
#define SRST_A_VOP1_NOC 273
#define SRST_A_VOP0 274
#define SRST_A_VOP1 275
#define SRST_H_VOP0_NOC 276
#define SRST_H_VOP1_NOC 277
#define SRST_H_VOP0 278
#define SRST_H_VOP1 279
#define SRST_D_VOP0 280
#define SRST_D_VOP1 281
#define SRST_VOP0_PWM 282
#define SRST_VOP1_PWM 283
#define SRST_P_EDP_NOC 284
#define SRST_P_EDP_CTRL 285
/* cru_softrst_con18 */
#define SRST_A_GPU 288
#define SRST_A_GPU_NOC 289
#define SRST_A_GPU_GRF 290
#define SRST_PVTM_GPU 291
#define SRST_A_USB3_NOC 292
#define SRST_A_USB3_OTG0 293
#define SRST_A_USB3_OTG1 294
#define SRST_A_USB3_GRF 295
#define SRST_PMU 296
/* cru_softrst_con19 */
#define SRST_P_TIMER0_5 304
#define SRST_TIMER0 305
#define SRST_TIMER1 306
#define SRST_TIMER2 307
#define SRST_TIMER3 308
#define SRST_TIMER4 309
#define SRST_TIMER5 310
#define SRST_P_TIMER6_11 311
#define SRST_TIMER6 312
#define SRST_TIMER7 313
#define SRST_TIMER8 314
#define SRST_TIMER9 315
#define SRST_TIMER10 316
#define SRST_TIMER11 317
#define SRST_P_INTR_ARB_PMU 318
#define SRST_P_ALIVE_SGRF 319
/* cru_softrst_con20 */
#define SRST_P_GPIO2 320
#define SRST_P_GPIO3 321
#define SRST_P_GPIO4 322
#define SRST_P_GRF 323
#define SRST_P_ALIVE_NOC 324
#define SRST_P_WDT0 325
#define SRST_P_WDT1 326
#define SRST_P_INTR_ARB 327
#define SRST_P_UPHY0_DPTX 328
#define SRST_P_UPHY0_APB 330
#define SRST_P_UPHY0_TCPHY 332
#define SRST_P_UPHY1_TCPHY 333
#define SRST_P_UPHY0_TCPDCTRL 334
#define SRST_P_UPHY1_TCPDCTRL 335
/* pmu soft-reset indices */
/* pmu_cru_softrst_con0 */
#define SRST_P_NOC 0
#define SRST_P_INTMEM 1
#define SRST_H_CM0S 2
#define SRST_H_CM0S_NOC 3
#define SRST_DBG_CM0S 4
#define SRST_PO_CM0S 5
#define SRST_P_SPI6 6
#define SRST_SPI6 7
#define SRST_P_TIMER_0_1 8
#define SRST_P_TIMER_0 9
#define SRST_P_TIMER_1 10
#define SRST_P_UART4 11
#define SRST_UART4 12
#define SRST_P_WDT 13
/* pmu_cru_softrst_con1 */
#define SRST_P_I2C6 16
#define SRST_P_I2C7 17
#define SRST_P_I2C8 18
#define SRST_P_MAILBOX 19
#define SRST_P_RKPWM 20
#define SRST_P_PMUGRF 21
#define SRST_P_SGRF 22
#define SRST_P_GPIO0 23
#define SRST_P_GPIO1 24
#define SRST_P_CRU 25
#define SRST_P_INTR 26
#define SRST_PVTM 27
#define SRST_I2C6 28
#define SRST_I2C7 29
#define SRST_I2C8 30
#endif
include/dt-bindings/gpio/tegra-gpio.h
View file @ 2ec3240f
......@@ -12,40 +12,40 @@
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_BANK_ID_A 0
#define TEGRA_GPIO_BANK_ID_B 1
#define TEGRA_GPIO_BANK_ID_C 2
#define TEGRA_GPIO_BANK_ID_D 3
#define TEGRA_GPIO_BANK_ID_E 4
#define TEGRA_GPIO_BANK_ID_F 5
#define TEGRA_GPIO_BANK_ID_G 6
#define TEGRA_GPIO_BANK_ID_H 7
#define TEGRA_GPIO_BANK_ID_I 8
#define TEGRA_GPIO_BANK_ID_J 9
#define TEGRA_GPIO_BANK_ID_K 10
#define TEGRA_GPIO_BANK_ID_L 11
#define TEGRA_GPIO_BANK_ID_M 12
#define TEGRA_GPIO_BANK_ID_N 13
#define TEGRA_GPIO_BANK_ID_O 14
#define TEGRA_GPIO_BANK_ID_P 15
#define TEGRA_GPIO_BANK_ID_Q 16
#define TEGRA_GPIO_BANK_ID_R 17
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO_BANK_ID_T 19
#define TEGRA_GPIO_BANK_ID_U 20
#define TEGRA_GPIO_BANK_ID_V 21
#define TEGRA_GPIO_BANK_ID_W 22
#define TEGRA_GPIO_BANK_ID_X 23
#define TEGRA_GPIO_BANK_ID_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31
#define TEGRA_GPIO_PORT_A 0
#define TEGRA_GPIO_PORT_B 1
#define TEGRA_GPIO_PORT_C 2
#define TEGRA_GPIO_PORT_D 3
#define TEGRA_GPIO_PORT_E 4
#define TEGRA_GPIO_PORT_F 5
#define TEGRA_GPIO_PORT_G 6
#define TEGRA_GPIO_PORT_H 7
#define TEGRA_GPIO_PORT_I 8
#define TEGRA_GPIO_PORT_J 9
#define TEGRA_GPIO_PORT_K 10
#define TEGRA_GPIO_PORT_L 11
#define TEGRA_GPIO_PORT_M 12
#define TEGRA_GPIO_PORT_N 13
#define TEGRA_GPIO_PORT_O 14
#define TEGRA_GPIO_PORT_P 15
#define TEGRA_GPIO_PORT_Q 16
#define TEGRA_GPIO_PORT_R 17
#define TEGRA_GPIO_PORT_S 18
#define TEGRA_GPIO_PORT_T 19
#define TEGRA_GPIO_PORT_U 20
#define TEGRA_GPIO_PORT_V 21
#define TEGRA_GPIO_PORT_W 22
#define TEGRA_GPIO_PORT_X 23
#define TEGRA_GPIO_PORT_Y 24
#define TEGRA_GPIO_PORT_Z 25
#define TEGRA_GPIO_PORT_AA 26
#define TEGRA_GPIO_PORT_BB 27
#define TEGRA_GPIO_PORT_CC 28
#define TEGRA_GPIO_PORT_DD 29
#define TEGRA_GPIO_PORT_EE 30
#define TEGRA_GPIO_PORT_FF 31
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
#define TEGRA_GPIO(port, offset) \
((TEGRA_GPIO_PORT_##port * 8) + offset)
#endif
include/dt-bindings/gpio/tegra186-gpio.h 0 → 100644
View file @ 2ec3240f
/*
* This header provides constants for binding nvidia,tegra186-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA_MAIN_GPIO_PORT_A 0
#define TEGRA_MAIN_GPIO_PORT_B 1
#define TEGRA_MAIN_GPIO_PORT_C 2
#define TEGRA_MAIN_GPIO_PORT_D 3
#define TEGRA_MAIN_GPIO_PORT_E 4
#define TEGRA_MAIN_GPIO_PORT_F 5
#define TEGRA_MAIN_GPIO_PORT_G 6
#define TEGRA_MAIN_GPIO_PORT_H 7
#define TEGRA_MAIN_GPIO_PORT_I 8
#define TEGRA_MAIN_GPIO_PORT_J 9
#define TEGRA_MAIN_GPIO_PORT_K 10
#define TEGRA_MAIN_GPIO_PORT_L 11
#define TEGRA_MAIN_GPIO_PORT_M 12
#define TEGRA_MAIN_GPIO_PORT_N 13
#define TEGRA_MAIN_GPIO_PORT_O 14
#define TEGRA_MAIN_GPIO_PORT_P 15
#define TEGRA_MAIN_GPIO_PORT_Q 16
#define TEGRA_MAIN_GPIO_PORT_R 17
#define TEGRA_MAIN_GPIO_PORT_T 18
#define TEGRA_MAIN_GPIO_PORT_X 19
#define TEGRA_MAIN_GPIO_PORT_Y 20
#define TEGRA_MAIN_GPIO_PORT_BB 21
#define TEGRA_MAIN_GPIO_PORT_CC 22
#define TEGRA_MAIN_GPIO(port, offset) \
((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA_AON_GPIO_PORT_S 0
#define TEGRA_AON_GPIO_PORT_U 1
#define TEGRA_AON_GPIO_PORT_V 2
#define TEGRA_AON_GPIO_PORT_W 3
#define TEGRA_AON_GPIO_PORT_Z 4
#define TEGRA_AON_GPIO_PORT_AA 5
#define TEGRA_AON_GPIO_PORT_EE 6
#define TEGRA_AON_GPIO_PORT_FF 7
#define TEGRA_AON_GPIO(port, offset) \
((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
#endif
include/dt-bindings/pinctrl/hisi.h 0 → 100644
View file @ 2ec3240f
/*
* This header provides constants for hisilicon pinctrl bindings.
*
* Copyright (c) 2015 Hisilicon Limited.
* Copyright (c) 2015 Linaro Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_PINCTRL_HISI_H
#define _DT_BINDINGS_PINCTRL_HISI_H
/* iomg bit definition */
#define MUX_M0 0
#define MUX_M1 1
#define MUX_M2 2
#define MUX_M3 3
#define MUX_M4 4
#define MUX_M5 5
#define MUX_M6 6
#define MUX_M7 7
/* iocg bit definition */
#define PULL_MASK (3)
#define PULL_DIS (0)
#define PULL_UP (1 << 0)
#define PULL_DOWN (1 << 1)
/* drive strength definition */
#define DRIVE_MASK (7 << 4)
#define DRIVE1_02MA (0 << 4)
#define DRIVE1_04MA (1 << 4)
#define DRIVE1_08MA (2 << 4)
#define DRIVE1_10MA (3 << 4)
#define DRIVE2_02MA (0 << 4)
#define DRIVE2_04MA (1 << 4)
#define DRIVE2_08MA (2 << 4)
#define DRIVE2_10MA (3 << 4)
#define DRIVE3_04MA (0 << 4)
#define DRIVE3_08MA (1 << 4)
#define DRIVE3_12MA (2 << 4)
#define DRIVE3_16MA (3 << 4)
#define DRIVE3_20MA (4 << 4)
#define DRIVE3_24MA (5 << 4)
#define DRIVE3_32MA (6 << 4)
#define DRIVE3_40MA (7 << 4)
#define DRIVE4_02MA (0 << 4)
#define DRIVE4_04MA (2 << 4)
#define DRIVE4_08MA (4 << 4)
#define DRIVE4_10MA (6 << 4)
#endif
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