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Commit 3393d422 authored by Stephen Warren's avatar Stephen Warren
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ARM: tegra: update DT files to add reset properties 

An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.

Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent ed520c90
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Showing with 266 additions and 4 deletions
arch/arm/boot/dts/tegra114.dtsi
View file @ 3393d422
...@@ -43,6 +43,7 @@ tegra_car: clock { ...@@ -43,6 +43,7 @@ tegra_car: clock {
compatible = "nvidia,tegra114-car"; compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>; reg = <0x60006000 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
apbdma: dma { apbdma: dma {
...@@ -81,6 +82,8 @@ apbdma: dma { ...@@ -81,6 +82,8 @@ apbdma: dma {
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_APBDMA>; clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
resets = <&tegra_car 34>;
reset-names = "dma";
}; };
ahb: ahb { ahb: ahb {
...@@ -125,8 +128,10 @@ uarta: serial@70006000 { ...@@ -125,8 +128,10 @@ uarta: serial@70006000 {
reg-shift = <2>; reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>; nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled";
clocks = <&tegra_car TEGRA114_CLK_UARTA>; clocks = <&tegra_car TEGRA114_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
status = "disabled";
}; };
uartb: serial@70006040 { uartb: serial@70006040 {
...@@ -135,8 +140,10 @@ uartb: serial@70006040 { ...@@ -135,8 +140,10 @@ uartb: serial@70006040 {
reg-shift = <2>; reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>; nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled";
clocks = <&tegra_car TEGRA114_CLK_UARTB>; clocks = <&tegra_car TEGRA114_CLK_UARTB>;
resets = <&tegra_car 7>;
reset-names = "serial";
status = "disabled";
}; };
uartc: serial@70006200 { uartc: serial@70006200 {
...@@ -145,8 +152,10 @@ uartc: serial@70006200 { ...@@ -145,8 +152,10 @@ uartc: serial@70006200 {
reg-shift = <2>; reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>; nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled";
clocks = <&tegra_car TEGRA114_CLK_UARTC>; clocks = <&tegra_car TEGRA114_CLK_UARTC>;
resets = <&tegra_car 55>;
reset-names = "serial";
status = "disabled";
}; };
uartd: serial@70006300 { uartd: serial@70006300 {
...@@ -155,8 +164,10 @@ uartd: serial@70006300 { ...@@ -155,8 +164,10 @@ uartd: serial@70006300 {
reg-shift = <2>; reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>; nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled";
clocks = <&tegra_car TEGRA114_CLK_UARTD>; clocks = <&tegra_car TEGRA114_CLK_UARTD>;
resets = <&tegra_car 65>;
reset-names = "serial";
status = "disabled";
}; };
pwm: pwm { pwm: pwm {
...@@ -164,6 +175,8 @@ pwm: pwm { ...@@ -164,6 +175,8 @@ pwm: pwm {
reg = <0x7000a000 0x100>; reg = <0x7000a000 0x100>;
#pwm-cells = <2>; #pwm-cells = <2>;
clocks = <&tegra_car TEGRA114_CLK_PWM>; clocks = <&tegra_car TEGRA114_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled"; status = "disabled";
}; };
...@@ -175,6 +188,8 @@ i2c@7000c000 { ...@@ -175,6 +188,8 @@ i2c@7000c000 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_I2C1>; clocks = <&tegra_car TEGRA114_CLK_I2C1>;
clock-names = "div-clk"; clock-names = "div-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -186,6 +201,8 @@ i2c@7000c400 { ...@@ -186,6 +201,8 @@ i2c@7000c400 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_I2C2>; clocks = <&tegra_car TEGRA114_CLK_I2C2>;
clock-names = "div-clk"; clock-names = "div-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -197,6 +214,8 @@ i2c@7000c500 { ...@@ -197,6 +214,8 @@ i2c@7000c500 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_I2C3>; clocks = <&tegra_car TEGRA114_CLK_I2C3>;
clock-names = "div-clk"; clock-names = "div-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -208,6 +227,8 @@ i2c@7000c700 { ...@@ -208,6 +227,8 @@ i2c@7000c700 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_I2C4>; clocks = <&tegra_car TEGRA114_CLK_I2C4>;
clock-names = "div-clk"; clock-names = "div-clk";
resets = <&tegra_car 103>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -219,6 +240,8 @@ i2c@7000d000 { ...@@ -219,6 +240,8 @@ i2c@7000d000 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_I2C5>; clocks = <&tegra_car TEGRA114_CLK_I2C5>;
clock-names = "div-clk"; clock-names = "div-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -231,6 +254,8 @@ spi@7000d400 { ...@@ -231,6 +254,8 @@ spi@7000d400 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC1>; clocks = <&tegra_car TEGRA114_CLK_SBC1>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 41>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -243,6 +268,8 @@ spi@7000d600 { ...@@ -243,6 +268,8 @@ spi@7000d600 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC2>; clocks = <&tegra_car TEGRA114_CLK_SBC2>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -255,6 +282,8 @@ spi@7000d800 { ...@@ -255,6 +282,8 @@ spi@7000d800 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC3>; clocks = <&tegra_car TEGRA114_CLK_SBC3>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 46>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -267,6 +296,8 @@ spi@7000da00 { ...@@ -267,6 +296,8 @@ spi@7000da00 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC4>; clocks = <&tegra_car TEGRA114_CLK_SBC4>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 68>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -279,6 +310,8 @@ spi@7000dc00 { ...@@ -279,6 +310,8 @@ spi@7000dc00 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC5>; clocks = <&tegra_car TEGRA114_CLK_SBC5>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 104>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -291,6 +324,8 @@ spi@7000de00 { ...@@ -291,6 +324,8 @@ spi@7000de00 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA114_CLK_SBC6>; clocks = <&tegra_car TEGRA114_CLK_SBC6>;
clock-names = "spi"; clock-names = "spi";
resets = <&tegra_car 105>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -306,6 +341,8 @@ kbc { ...@@ -306,6 +341,8 @@ kbc {
reg = <0x7000e200 0x100>; reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_KBC>; clocks = <&tegra_car TEGRA114_CLK_KBC>;
resets = <&tegra_car 36>;
reset-names = "kbc";
status = "disabled"; status = "disabled";
}; };
...@@ -353,6 +390,22 @@ ahub { ...@@ -353,6 +390,22 @@ ahub {
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2", "i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif_in", "amx", "adx"; "spdif_in", "amx", "adx";
resets = <&tegra_car 106>, /* d_audio */
<&tegra_car 107>, /* apbif */
<&tegra_car 30>, /* i2s0 */
<&tegra_car 11>, /* i2s1 */
<&tegra_car 18>, /* i2s2 */
<&tegra_car 101>, /* i2s3 */
<&tegra_car 102>, /* i2s4 */
<&tegra_car 108>, /* dam0 */
<&tegra_car 109>, /* dam1 */
<&tegra_car 110>, /* dam2 */
<&tegra_car 10>, /* spdif */
<&tegra_car 153>, /* amx */
<&tegra_car 154>; /* adx */
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif", "amx", "adx";
ranges; ranges;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -362,6 +415,8 @@ tegra_i2s0: i2s@70080300 { ...@@ -362,6 +415,8 @@ tegra_i2s0: i2s@70080300 {
reg = <0x70080300 0x100>; reg = <0x70080300 0x100>;
nvidia,ahub-cif-ids = <4 4>; nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car TEGRA114_CLK_I2S0>; clocks = <&tegra_car TEGRA114_CLK_I2S0>;
resets = <&tegra_car 30>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -370,6 +425,8 @@ tegra_i2s1: i2s@70080400 { ...@@ -370,6 +425,8 @@ tegra_i2s1: i2s@70080400 {
reg = <0x70080400 0x100>; reg = <0x70080400 0x100>;
nvidia,ahub-cif-ids = <5 5>; nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car TEGRA114_CLK_I2S1>; clocks = <&tegra_car TEGRA114_CLK_I2S1>;
resets = <&tegra_car 11>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -378,6 +435,8 @@ tegra_i2s2: i2s@70080500 { ...@@ -378,6 +435,8 @@ tegra_i2s2: i2s@70080500 {
reg = <0x70080500 0x100>; reg = <0x70080500 0x100>;
nvidia,ahub-cif-ids = <6 6>; nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car TEGRA114_CLK_I2S2>; clocks = <&tegra_car TEGRA114_CLK_I2S2>;
resets = <&tegra_car 18>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -386,6 +445,8 @@ tegra_i2s3: i2s@70080600 { ...@@ -386,6 +445,8 @@ tegra_i2s3: i2s@70080600 {
reg = <0x70080600 0x100>; reg = <0x70080600 0x100>;
nvidia,ahub-cif-ids = <7 7>; nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car TEGRA114_CLK_I2S3>; clocks = <&tegra_car TEGRA114_CLK_I2S3>;
resets = <&tegra_car 101>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -394,6 +455,8 @@ tegra_i2s4: i2s@70080700 { ...@@ -394,6 +455,8 @@ tegra_i2s4: i2s@70080700 {
reg = <0x70080700 0x100>; reg = <0x70080700 0x100>;
nvidia,ahub-cif-ids = <8 8>; nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car TEGRA114_CLK_I2S4>; clocks = <&tegra_car TEGRA114_CLK_I2S4>;
resets = <&tegra_car 102>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -403,6 +466,8 @@ sdhci@78000000 { ...@@ -403,6 +466,8 @@ sdhci@78000000 {
reg = <0x78000000 0x200>; reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disable"; status = "disable";
}; };
...@@ -411,6 +476,8 @@ sdhci@78000200 { ...@@ -411,6 +476,8 @@ sdhci@78000200 {
reg = <0x78000200 0x200>; reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disable"; status = "disable";
}; };
...@@ -419,6 +486,8 @@ sdhci@78000400 { ...@@ -419,6 +486,8 @@ sdhci@78000400 {
reg = <0x78000400 0x200>; reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disable"; status = "disable";
}; };
...@@ -427,6 +496,8 @@ sdhci@78000600 { ...@@ -427,6 +496,8 @@ sdhci@78000600 {
reg = <0x78000600 0x200>; reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disable"; status = "disable";
}; };
...@@ -436,6 +507,8 @@ usb@7d000000 { ...@@ -436,6 +507,8 @@ usb@7d000000 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi"; phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USBD>; clocks = <&tegra_car TEGRA114_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,phy = <&phy1>; nvidia,phy = <&phy1>;
status = "disabled"; status = "disabled";
}; };
...@@ -467,6 +540,8 @@ usb@7d008000 { ...@@ -467,6 +540,8 @@ usb@7d008000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi"; phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USB3>; clocks = <&tegra_car TEGRA114_CLK_USB3>;
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>; nvidia,phy = <&phy3>;
status = "disabled"; status = "disabled";
}; };
......
arch/arm/boot/dts/tegra20-paz00.dts
View file @ 3393d422
...@@ -280,6 +280,8 @@ nvec { ...@@ -280,6 +280,8 @@ nvec {
clocks = <&tegra_car TEGRA20_CLK_I2C3>, clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>; <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk"; clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
}; };
i2c@7000d000 { i2c@7000d000 {
......
arch/arm/boot/dts/tegra20.dtsi
View file @ 3393d422
...@@ -22,6 +22,8 @@ host1x { ...@@ -22,6 +22,8 @@ host1x {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
resets = <&tegra_car 28>;
reset-names = "host1x";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -33,6 +35,8 @@ mpe { ...@@ -33,6 +35,8 @@ mpe {
reg = <0x54040000 0x00040000>; reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_MPE>; clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
}; };
vi { vi {
...@@ -40,6 +44,8 @@ vi { ...@@ -40,6 +44,8 @@ vi {
reg = <0x54080000 0x00040000>; reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>; clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
}; };
epp { epp {
...@@ -47,6 +53,8 @@ epp { ...@@ -47,6 +53,8 @@ epp {
reg = <0x540c0000 0x00040000>; reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EPP>; clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
}; };
isp { isp {
...@@ -54,6 +62,8 @@ isp { ...@@ -54,6 +62,8 @@ isp {
reg = <0x54100000 0x00040000>; reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_ISP>; clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
}; };
gr2d { gr2d {
...@@ -61,12 +71,16 @@ gr2d { ...@@ -61,12 +71,16 @@ gr2d {
reg = <0x54140000 0x00040000>; reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>; clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
}; };
gr3d { gr3d {
compatible = "nvidia,tegra20-gr3d"; compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>; reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>; clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
}; };
dc@54200000 { dc@54200000 {
...@@ -76,6 +90,8 @@ dc@54200000 { ...@@ -76,6 +90,8 @@ dc@54200000 {
clocks = <&tegra_car TEGRA20_CLK_DISP1>, clocks = <&tegra_car TEGRA20_CLK_DISP1>,
<&tegra_car TEGRA20_CLK_PLL_P>; <&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent"; clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
rgb { rgb {
status = "disabled"; status = "disabled";
...@@ -89,6 +105,8 @@ dc@54240000 { ...@@ -89,6 +105,8 @@ dc@54240000 {
clocks = <&tegra_car TEGRA20_CLK_DISP2>, clocks = <&tegra_car TEGRA20_CLK_DISP2>,
<&tegra_car TEGRA20_CLK_PLL_P>; <&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent"; clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
rgb { rgb {
status = "disabled"; status = "disabled";
...@@ -102,6 +120,8 @@ hdmi { ...@@ -102,6 +120,8 @@ hdmi {
clocks = <&tegra_car TEGRA20_CLK_HDMI>, clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>; <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent"; clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
status = "disabled"; status = "disabled";
}; };
...@@ -117,6 +137,8 @@ dsi { ...@@ -117,6 +137,8 @@ dsi {
compatible = "nvidia,tegra20-dsi"; compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>; reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>; clocks = <&tegra_car TEGRA20_CLK_DSI>;
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -160,6 +182,7 @@ tegra_car: clock { ...@@ -160,6 +182,7 @@ tegra_car: clock {
compatible = "nvidia,tegra20-car"; compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>; reg = <0x60006000 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
apbdma: dma { apbdma: dma {
...@@ -182,6 +205,8 @@ apbdma: dma { ...@@ -182,6 +205,8 @@ apbdma: dma {
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_APBDMA>; clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
resets = <&tegra_car 34>;
reset-names = "dma";
}; };
ahb { ahb {
...@@ -224,6 +249,8 @@ tegra_ac97: ac97 { ...@@ -224,6 +249,8 @@ tegra_ac97: ac97 {
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>; nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car TEGRA20_CLK_AC97>; clocks = <&tegra_car TEGRA20_CLK_AC97>;
resets = <&tegra_car 3>;
reset-names = "ac97";
status = "disabled"; status = "disabled";
}; };
...@@ -233,6 +260,8 @@ tegra_i2s1: i2s@70002800 { ...@@ -233,6 +260,8 @@ tegra_i2s1: i2s@70002800 {
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>; nvidia,dma-request-selector = <&apbdma 2>;
clocks = <&tegra_car TEGRA20_CLK_I2S1>; clocks = <&tegra_car TEGRA20_CLK_I2S1>;
resets = <&tegra_car 11>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -242,6 +271,8 @@ tegra_i2s2: i2s@70002a00 { ...@@ -242,6 +271,8 @@ tegra_i2s2: i2s@70002a00 {
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>; nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car TEGRA20_CLK_I2S2>; clocks = <&tegra_car TEGRA20_CLK_I2S2>;
resets = <&tegra_car 18>;
reset-names = "i2s";
status = "disabled"; status = "disabled";
}; };
...@@ -259,6 +290,8 @@ uarta: serial@70006000 { ...@@ -259,6 +290,8 @@ uarta: serial@70006000 {
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>; nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car TEGRA20_CLK_UARTA>; clocks = <&tegra_car TEGRA20_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
...@@ -269,6 +302,8 @@ uartb: serial@70006040 { ...@@ -269,6 +302,8 @@ uartb: serial@70006040 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>; nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car TEGRA20_CLK_UARTB>; clocks = <&tegra_car TEGRA20_CLK_UARTB>;
resets = <&tegra_car 7>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
...@@ -279,6 +314,8 @@ uartc: serial@70006200 { ...@@ -279,6 +314,8 @@ uartc: serial@70006200 {
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>; nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car TEGRA20_CLK_UARTC>; clocks = <&tegra_car TEGRA20_CLK_UARTC>;
resets = <&tegra_car 55>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
...@@ -289,6 +326,8 @@ uartd: serial@70006300 { ...@@ -289,6 +326,8 @@ uartd: serial@70006300 {
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>; nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car TEGRA20_CLK_UARTD>; clocks = <&tegra_car TEGRA20_CLK_UARTD>;
resets = <&tegra_car 65>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
...@@ -299,6 +338,8 @@ uarte: serial@70006400 { ...@@ -299,6 +338,8 @@ uarte: serial@70006400 {
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>; nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car TEGRA20_CLK_UARTE>; clocks = <&tegra_car TEGRA20_CLK_UARTE>;
resets = <&tegra_car 66>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
...@@ -307,6 +348,8 @@ pwm: pwm { ...@@ -307,6 +348,8 @@ pwm: pwm {
reg = <0x7000a000 0x100>; reg = <0x7000a000 0x100>;
#pwm-cells = <2>; #pwm-cells = <2>;
clocks = <&tegra_car TEGRA20_CLK_PWM>; clocks = <&tegra_car TEGRA20_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled"; status = "disabled";
}; };
...@@ -326,6 +369,8 @@ i2c@7000c000 { ...@@ -326,6 +369,8 @@ i2c@7000c000 {
clocks = <&tegra_car TEGRA20_CLK_I2C1>, clocks = <&tegra_car TEGRA20_CLK_I2C1>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>; <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk"; clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -337,6 +382,8 @@ spi@7000c380 { ...@@ -337,6 +382,8 @@ spi@7000c380 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SPI>; clocks = <&tegra_car TEGRA20_CLK_SPI>;
resets = <&tegra_car 43>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -349,6 +396,8 @@ i2c@7000c400 { ...@@ -349,6 +396,8 @@ i2c@7000c400 {
clocks = <&tegra_car TEGRA20_CLK_I2C2>, clocks = <&tegra_car TEGRA20_CLK_I2C2>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>; <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk"; clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -361,6 +410,8 @@ i2c@7000c500 { ...@@ -361,6 +410,8 @@ i2c@7000c500 {
clocks = <&tegra_car TEGRA20_CLK_I2C3>, clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>; <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk"; clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -373,6 +424,8 @@ i2c@7000d000 { ...@@ -373,6 +424,8 @@ i2c@7000d000 {
clocks = <&tegra_car TEGRA20_CLK_DVC>, clocks = <&tegra_car TEGRA20_CLK_DVC>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>; <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk"; clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -384,6 +437,8 @@ spi@7000d400 { ...@@ -384,6 +437,8 @@ spi@7000d400 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC1>; clocks = <&tegra_car TEGRA20_CLK_SBC1>;
resets = <&tegra_car 41>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -395,6 +450,8 @@ spi@7000d600 { ...@@ -395,6 +450,8 @@ spi@7000d600 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC2>; clocks = <&tegra_car TEGRA20_CLK_SBC2>;
resets = <&tegra_car 44>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -406,6 +463,8 @@ spi@7000d800 { ...@@ -406,6 +463,8 @@ spi@7000d800 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC3>; clocks = <&tegra_car TEGRA20_CLK_SBC3>;
resets = <&tegra_car 46>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -417,6 +476,8 @@ spi@7000da00 { ...@@ -417,6 +476,8 @@ spi@7000da00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC4>; clocks = <&tegra_car TEGRA20_CLK_SBC4>;
resets = <&tegra_car 68>;
reset-names = "spi";
status = "disabled"; status = "disabled";
}; };
...@@ -425,6 +486,8 @@ kbc { ...@@ -425,6 +486,8 @@ kbc {
reg = <0x7000e200 0x100>; reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_KBC>; clocks = <&tegra_car TEGRA20_CLK_KBC>;
resets = <&tegra_car 36>;
reset-names = "kbc";
status = "disabled"; status = "disabled";
}; };
...@@ -481,6 +544,10 @@ pcie-controller { ...@@ -481,6 +544,10 @@ pcie-controller {
<&tegra_car TEGRA20_CLK_PCIE_XCLK>, <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
<&tegra_car TEGRA20_CLK_PLL_E>; <&tegra_car TEGRA20_CLK_PLL_E>;
clock-names = "pex", "afi", "pcie_xclk", "pll_e"; clock-names = "pex", "afi", "pcie_xclk", "pll_e";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
status = "disabled"; status = "disabled";
pci@1,0 { pci@1,0 {
...@@ -517,6 +584,8 @@ usb@c5000000 { ...@@ -517,6 +584,8 @@ usb@c5000000 {
phy_type = "utmi"; phy_type = "utmi";
nvidia,has-legacy-mode; nvidia,has-legacy-mode;
clocks = <&tegra_car TEGRA20_CLK_USBD>; clocks = <&tegra_car TEGRA20_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,needs-double-reset; nvidia,needs-double-reset;
nvidia,phy = <&phy1>; nvidia,phy = <&phy1>;
status = "disabled"; status = "disabled";
...@@ -548,6 +617,8 @@ usb@c5004000 { ...@@ -548,6 +617,8 @@ usb@c5004000 {
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi"; phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>; clocks = <&tegra_car TEGRA20_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>; nvidia,phy = <&phy2>;
status = "disabled"; status = "disabled";
}; };
...@@ -569,6 +640,8 @@ usb@c5008000 { ...@@ -569,6 +640,8 @@ usb@c5008000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi"; phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USB3>; clocks = <&tegra_car TEGRA20_CLK_USB3>;
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>; nvidia,phy = <&phy3>;
status = "disabled"; status = "disabled";
}; };
...@@ -597,6 +670,8 @@ sdhci@c8000000 { ...@@ -597,6 +670,8 @@ sdhci@c8000000 {
reg = <0xc8000000 0x200>; reg = <0xc8000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled"; status = "disabled";
}; };
...@@ -605,6 +680,8 @@ sdhci@c8000200 { ...@@ -605,6 +680,8 @@ sdhci@c8000200 {
reg = <0xc8000200 0x200>; reg = <0xc8000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled"; status = "disabled";
}; };
...@@ -613,6 +690,8 @@ sdhci@c8000400 { ...@@ -613,6 +690,8 @@ sdhci@c8000400 {
reg = <0xc8000400 0x200>; reg = <0xc8000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled"; status = "disabled";
}; };
...@@ -621,6 +700,8 @@ sdhci@c8000600 { ...@@ -621,6 +700,8 @@ sdhci@c8000600 {
reg = <0xc8000600 0x200>; reg = <0xc8000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled"; status = "disabled";
}; };
......
arch/arm/boot/dts/tegra30.dtsi
View file @ 3393d422
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