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Commit 3439633a authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next 

Rather large pull request this time around, due to the long-pending
cleanup of the kernel driver being here.  There's a stupidly large
number of commits for that, as I wanted to have the series be
bisectable at a fairly fine-grained level.  That said, a very large
portion of the churn in the rework was automated, and a very large
number of boards from right across the whole range we support have
been tested.  I'm fairly confident there shouldn't be (too many)
issues from this.

Beyond correcting some not-so-great design decisions and making the
code a lot easier to work with, there's not much exciting (lower
memory usage, GPU VM should be a lot faster, etc) to be gained by the
end-user as a result of the cleanup, it mostly lays the groundwork for
future improvements.

A big thanks goes to Alexandre Courbot for testing/debugging the GK20A
codepaths for me :)

Highlights:
- A heap of perfmon work, providing a more useful userspace interface
and specifying counters for a bunch of boards
- Support for GT200 reclocking + other misc pm improvements
- Initial patches towards supporting GM20B (Tegra X1)
- Maxwell DisplayPort fixes
- Cleanup of the kernel driver
- The usual collection of random fixes

* 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (312 commits)
  drm/nouveau: bump driver version for release
  drm/nouveau/tegra: merge platform setup from nouveau drm
  drm/nouveau/pci: merge agp handling from nouveau drm
  drm/nouveau/device: remove pci/platform_device from common struct
  drm/nouveau/device: import pciid list and integrate quirks with it
  drm/nouveau/device: cleaner abstraction for device resource functions
  drm/nouveau/mc: move device irq handling to platform-specific code
  drm/nouveau/mc/gf100-: handle second interrupt tree
  drm/nouveau/mc: abstract interface to master intr registers
  drm/nouveau/pci: new subdev
  drm/nouveau/object: merge with handle
  drm/nouveau/core: remove the remainder of the previous style
  drm/nouveau/mpeg: convert to new-style nvkm_engine
  drm/nouveau/sw: convert to new-style nvkm_engine
  drm/nouveau/pm: convert to new-style nvkm_engine
  drm/nouveau/gr: convert to new-style nvkm_engine
  drm/nouveau/fifo: convert to new-style nvkm_engine
  drm/nouveau/disp: convert to new-style nvkm_engine
  drm/nouveau/dma: convert to new-style nvkm_engine
  drm/nouveau/cipher: convert to new-style nvkm_engine
  ...
parents d7b27368 a3c1ff87
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Showing with 43062 additions and 36467 deletions
drivers/gpu/drm/nouveau/Kbuild
View file @ 3439633a
......@@ -18,7 +18,6 @@ nouveau-y += $(nvkm-y)
ifdef CONFIG_X86
nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
endif
nouveau-y += nouveau_agp.o
nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
nouveau-y += nouveau_drm.o
nouveau-y += nouveau_hwmon.o
......
drivers/gpu/drm/nouveau/dispnv04/arb.c
View file @ 3439633a
......@@ -198,7 +198,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
int *burst, int *lwm)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nv_fifo_info fifo_data;
struct nv_sim_state sim_data;
int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
......
drivers/gpu/drm/nouveau/dispnv04/dac.c
View file @ 3439633a
......@@ -65,8 +65,8 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2])
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_object *device = &drm->device.object;
int i;
for (i = 0; i < 2; i++) {
......@@ -80,17 +80,22 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
* use a 10ms timeout (guards against crtc being inactive, in
* which case blank state would never change)
*/
if (!nvkm_timer_wait_eq(ptimer, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000000))
if (nvif_msec(&drm->device, 10,
if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
break;
) < 0)
return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000001))
if (nvif_msec(&drm->device, 10,
if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
break;
) < 0)
return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000000))
if (nvif_msec(&drm->device, 10,
if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
break;
) < 0)
return -EBUSY;
udelay(100);
......@@ -128,7 +133,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct drm_device *dev = encoder->dev;
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
uint8_t saved_palette0[3], saved_palette_mask;
......@@ -231,8 +236,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvkm_gpio *gpio = nvxx_gpio(device);
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nvkm_gpio *gpio = nvxx_gpio(&drm->device);
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
......@@ -265,10 +270,10 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
}
if (gpio) {
saved_gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
saved_gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV);
saved_gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
saved_gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV);
}
msleep(4);
......@@ -320,8 +325,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
if (gpio) {
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0);
}
return sample;
......
drivers/gpu/drm/nouveau/dispnv04/dfp.c
View file @ 3439633a
......@@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = encoder->dev;
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
......@@ -493,11 +493,11 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
if (mode == DRM_MODE_DPMS_ON) {
nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
} else {
nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
}
}
#endif
......@@ -624,8 +624,8 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nvkm_i2c_port *port = i2c->find(i2c, 2);
struct nvkm_i2c_board_info info[] = {
struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
struct nvkm_i2c_bus_probe info[] = {
{
{
.type = "sil164",
......@@ -639,16 +639,15 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
};
int type;
if (!nv_gf4_disp_arch(dev) || !port ||
get_tmds_slave(encoder))
if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
return;
type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL, NULL);
type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
if (type < 0)
return;
drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
&port->adapter, &info[type].dev);
&bus->i2c, &info[type].dev);
}
static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
......
drivers/gpu/drm/nouveau/dispnv04/disp.c
View file @ 3439633a
......@@ -47,7 +47,7 @@ nv04_display_create(struct drm_device *dev)
if (!disp)
return -ENOMEM;
nvif_object_map(nvif_object(&drm->device));
nvif_object_map(&drm->device.object);
nouveau_display(dev)->priv = disp;
nouveau_display(dev)->dtor = nv04_display_destroy;
......@@ -101,7 +101,9 @@ nv04_display_create(struct drm_device *dev)
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
nv_encoder->i2c = i2c->find(i2c, nv_encoder->dcb->i2c_index);
struct nvkm_i2c_bus *bus =
nvkm_i2c_bus_find(i2c, nv_encoder->dcb->i2c_index);
nv_encoder->i2c = bus ? &bus->i2c : NULL;
}
/* Save previous state */
......@@ -151,7 +153,7 @@ nv04_display_destroy(struct drm_device *dev)
nouveau_display(dev)->priv = NULL;
kfree(disp);
nvif_object_unmap(nvif_object(&drm->device));
nvif_object_unmap(&drm->device.object);
}
int
......
drivers/gpu/drm/nouveau/dispnv04/disp.h
View file @ 3439633a
......@@ -172,7 +172,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_bios *bios = nvxx_bios(&drm->device);
struct nvbios_init init = {
.subdev = nv_subdev(bios),
.subdev = &bios->subdev,
.bios = bios,
.offset = table,
.outp = outp,
......
drivers/gpu/drm/nouveau/dispnv04/hw.c
View file @ 3439633a
......@@ -165,8 +165,8 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
struct nvkm_pll_vals *pllvals)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nvkm_bios *bios = nvxx_bios(device);
struct nvif_object *device = &drm->device.object;
struct nvkm_bios *bios = nvxx_bios(&drm->device);
uint32_t reg1, pll1, pll2 = 0;
struct nvbios_pll pll_lim;
int ret;
......@@ -660,8 +660,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nvif_object *device = &drm->device.object;
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t reg900;
int i;
......@@ -678,10 +677,10 @@ nv_load_state_ext(struct drm_device *dev, int head,
nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
nvif_wr32(device, NV_PVIDEO_LIMIT(0), device->info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_LIMIT(1), device->info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), device->info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), device->info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
......@@ -741,8 +740,14 @@ nv_load_state_ext(struct drm_device *dev, int head,
if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
/* Not waiting for vertical retrace before modifying
CRE_53/CRE_54 causes lockups. */
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
nvif_msec(&drm->device, 650,
if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
break;
);
nvif_msec(&drm->device, 650,
if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
break;
);
}
wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
......@@ -765,7 +770,7 @@ static void
nv_save_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
int head_offset = head * NV_PRMDIO_SIZE, i;
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
......@@ -784,7 +789,7 @@ void
nouveau_hw_load_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
int head_offset = head * NV_PRMDIO_SIZE, i;
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
......
drivers/gpu/drm/nouveau/dispnv04/hw.h
View file @ 3439633a
......@@ -60,7 +60,7 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
static inline uint32_t NVReadCRTC(struct drm_device *dev,
int head, uint32_t reg)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint32_t val;
if (head)
reg += NV_PCRTC0_SIZE;
......@@ -71,7 +71,7 @@ static inline uint32_t NVReadCRTC(struct drm_device *dev,
static inline void NVWriteCRTC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (head)
reg += NV_PCRTC0_SIZE;
nvif_wr32(device, reg, val);
......@@ -80,7 +80,7 @@ static inline void NVWriteCRTC(struct drm_device *dev,
static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
int head, uint32_t reg)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint32_t val;
if (head)
reg += NV_PRAMDAC0_SIZE;
......@@ -91,7 +91,7 @@ static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
static inline void NVWriteRAMDAC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (head)
reg += NV_PRAMDAC0_SIZE;
nvif_wr32(device, reg, val);
......@@ -120,7 +120,7 @@ static inline void nv_write_tmds(struct drm_device *dev,
static inline void NVWriteVgaCrtc(struct drm_device *dev,
int head, uint8_t index, uint8_t value)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
}
......@@ -128,7 +128,7 @@ static inline void NVWriteVgaCrtc(struct drm_device *dev,
static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
int head, uint8_t index)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint8_t val;
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
......@@ -165,7 +165,7 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
int head, uint32_t reg)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t val;
......@@ -181,7 +181,7 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
static inline void NVWritePRMVIO(struct drm_device *dev,
int head, uint32_t reg, uint8_t value)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev);
/* Only NV4x have two pvio ranges; other twoHeads cards MUST call
......@@ -194,14 +194,14 @@ static inline void NVWritePRMVIO(struct drm_device *dev,
static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
}
static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
}
......@@ -209,7 +209,7 @@ static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
static inline void NVWriteVgaAttr(struct drm_device *dev,
int head, uint8_t index, uint8_t value)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (NVGetEnablePalette(dev, head))
index &= ~0x20;
else
......@@ -223,7 +223,7 @@ static inline void NVWriteVgaAttr(struct drm_device *dev,
static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
int head, uint8_t index)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint8_t val;
if (NVGetEnablePalette(dev, head))
index &= ~0x20;
......@@ -259,7 +259,7 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
static inline bool
nv_heads_tied(struct drm_device *dev)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev);
if (drm->device.info.chipset == 0x11)
......
drivers/gpu/drm/nouveau/dispnv04/overlay.c
View file @ 3439633a
......@@ -96,7 +96,8 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
struct nouveau_drm *drm = nouveau_drm(plane->dev);
struct nvif_object *dev = &drm->device.object;
struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base);
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
......@@ -118,7 +119,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
if (format > 0xffff)
return -ERANGE;
if (dev->info.chipset >= 0x30) {
if (drm->device.info.chipset >= 0x30) {
if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
return -ERANGE;
} else {
......@@ -173,7 +174,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int
nv10_disable_plane(struct drm_plane *plane)
{
struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base);
......@@ -197,7 +198,7 @@ nv_destroy_plane(struct drm_plane *plane)
static void
nv10_set_params(struct nouveau_plane *plane)
{
struct nvif_device *dev = &nouveau_drm(plane->base.dev)->device;
struct nvif_object *dev = &nouveau_drm(plane->base.dev)->device.object;
u32 luma = (plane->brightness - 512) << 16 | plane->contrast;
u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) |
(cos_mul(plane->hue, plane->saturation) & 0xffff);
......@@ -346,7 +347,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base);
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
......@@ -426,7 +427,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int
nv04_disable_plane(struct drm_plane *plane)
{
struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base);
......
drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
View file @ 3439633a
......@@ -35,7 +35,7 @@
#include <drm/i2c/ch7006.h>
static struct nvkm_i2c_board_info nv04_tv_encoder_info[] = {
static struct nvkm_i2c_bus_probe nv04_tv_encoder_info[] = {
{
{
I2C_BOARD_INFO("ch7006", 0x75),
......@@ -55,9 +55,13 @@ int nv04_tv_identify(struct drm_device *dev, int i2c_index)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
return i2c->identify(i2c, i2c_index, "TV encoder",
nv04_tv_encoder_info, NULL, NULL);
struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, i2c_index);
if (bus) {
return nvkm_i2c_bus_probe(bus, "TV encoder",
nv04_tv_encoder_info,
NULL, NULL);
}
return -ENODEV;
}
......@@ -205,7 +209,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
struct drm_device *dev = connector->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nvkm_i2c_port *port = i2c->find(i2c, entry->i2c_index);
struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, entry->i2c_index);
int type, ret;
/* Ensure that we can talk to this encoder */
......@@ -231,7 +235,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
/* Run the slave-specific initialization */
ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
&port->adapter,
&bus->i2c,
&nv04_tv_encoder_info[type].dev);
if (ret < 0)
goto fail_cleanup;
......
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
View file @ 3439633a
......@@ -62,8 +62,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
head = (dacclk & 0x100) >> 8;
/* Save the previous state. */
gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
......@@ -74,8 +74,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
/* Prepare the DAC for load detection. */
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
......@@ -120,8 +120,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
return sample;
}
......@@ -130,18 +130,10 @@ static bool
get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nvkm_device *device = nvxx_device(&drm->device);
/* Zotac FX5200 */
if (nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x1035) ||
nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x2035)) {
*pin_mask = 0xc;
return false;
}
/* MSI nForce2 IGP */
if (nv_device_match(nvxx_object(device), 0x01f0, 0x1462, 0x5710)) {
*pin_mask = 0xc;
if (device->quirk && device->quirk->tv_pin_mask) {
*pin_mask = device->quirk->tv_pin_mask;
return false;
}
......@@ -395,8 +387,8 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
nv_load_ptv(dev, regs, 200);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
}
......
drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
View file @ 3439633a
......@@ -131,13 +131,13 @@ static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
uint32_t val)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
nvif_wr32(device, reg, val);
nvif_wr32(&device->object, reg, val);
}
static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
{
struct nvif_device *device = &nouveau_drm(dev)->device;
return nvif_rd32(device, reg);
return nvif_rd32(&device->object, reg);
}
static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
......
drivers/gpu/drm/nouveau/include/nvif/client.h
View file @ 3439633a
......@@ -4,27 +4,17 @@
#include <nvif/object.h>
struct nvif_client {
struct nvif_object base;
struct nvif_object *object; /*XXX: hack for nvif_object() */
struct nvif_object object;
const struct nvif_driver *driver;
u64 version;
u8 route;
bool super;
};
static inline struct nvif_client *
nvif_client(struct nvif_object *object)
{
while (object && object->parent != object)
object = object->parent;
return (void *)object;
}
int nvif_client_init(void (*dtor)(struct nvif_client *), const char *,
const char *, u64, const char *, const char *,
int nvif_client_init(const char *drv, const char *name, u64 device,
const char *cfg, const char *dbg,
struct nvif_client *);
void nvif_client_fini(struct nvif_client *);
int nvif_client_new(const char *, const char *, u64, const char *,
const char *, struct nvif_client **);
void nvif_client_ref(struct nvif_client *, struct nvif_client **);
int nvif_client_ioctl(struct nvif_client *, void *, u32);
int nvif_client_suspend(struct nvif_client *);
int nvif_client_resume(struct nvif_client *);
......@@ -32,8 +22,7 @@ int nvif_client_resume(struct nvif_client *);
/*XXX*/
#include <core/client.h>
#define nvxx_client(a) ({ \
struct nvif_client *_client = nvif_client(nvif_object(a)); \
nvkm_client(_client->base.priv); \
struct nvif_client *_client = (a); \
(struct nvkm_client *)_client->object.priv; \
})
#endif
drivers/gpu/drm/nouveau/include/nvif/device.h
View file @ 3439633a
......@@ -5,26 +5,35 @@
#include <nvif/class.h>
struct nvif_device {
struct nvif_object base;
struct nvif_object *object; /*XXX: hack for nvif_object() */
struct nvif_object object;
struct nv_device_info_v0 info;
};
static inline struct nvif_device *
nvif_device(struct nvif_object *object)
{
while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ )
object = object->parent;
return (void *)object;
}
int nvif_device_init(struct nvif_object *, void (*dtor)(struct nvif_device *),
u32 handle, u32 oclass, void *, u32,
int nvif_device_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
struct nvif_device *);
void nvif_device_fini(struct nvif_device *);
int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass,
void *, u32, struct nvif_device **);
void nvif_device_ref(struct nvif_device *, struct nvif_device **);
u64 nvif_device_time(struct nvif_device *);
/* Delay based on GPU time (ie. PTIMER).
*
* Will return -ETIMEDOUT unless the loop was terminated with 'break',
* where it will return the number of nanoseconds taken instead.
*/
#define nvif_nsec(d,n,cond...) ({ \
struct nvif_device *_device = (d); \
u64 _nsecs = (n), _time0 = nvif_device_time(_device); \
s64 _taken = 0; \
\
do { \
cond \
} while (_taken = nvif_device_time(_device) - _time0, _taken < _nsecs);\
\
if (_taken >= _nsecs) \
_taken = -ETIMEDOUT; \
_taken; \
})
#define nvif_usec(d,u,cond...) nvif_nsec((d), (u) * 1000, ##cond)
#define nvif_msec(d,m,cond...) nvif_usec((d), (m) * 1000, ##cond)
/*XXX*/
#include <subdev/bios.h>
......@@ -36,26 +45,30 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <subdev/i2c.h>
#include <subdev/timer.h>
#include <subdev/therm.h>
#include <subdev/pci.h>
#define nvxx_device(a) nv_device(nvxx_object((a)))
#define nvxx_bios(a) nvkm_bios(nvxx_device(a))
#define nvxx_fb(a) nvkm_fb(nvxx_device(a))
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
#define nvxx_bar(a) nvkm_bar(nvxx_device(a))
#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))
#define nvxx_clk(a) nvkm_clk(nvxx_device(a))
#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))
#define nvxx_timer(a) nvkm_timer(nvxx_device(a))
#define nvxx_wait(a,b,c,d) nv_wait(nvxx_timer(a), (b), (c), (d))
#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c))
#define nvxx_therm(a) nvkm_therm(nvxx_device(a))
#define nvxx_device(a) ({ \
struct nvif_device *_device = (a); \
struct { \
struct nvkm_object object; \
struct nvkm_device *device; \
} *_udevice = _device->object.priv; \
_udevice->device; \
})
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvxx_device(a)->fb
#define nvxx_mmu(a) nvxx_device(a)->mmu
#define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvxx_device(a)->gpio
#define nvxx_clk(a) nvxx_device(a)->clk
#define nvxx_i2c(a) nvxx_device(a)->i2c
#define nvxx_therm(a) nvxx_device(a)->therm
#include <core/device.h>
#include <engine/fifo.h>
#include <engine/gr.h>
#include <engine/sw.h>
#define nvxx_fifo(a) nvkm_fifo(nvxx_device(a))
#define nvxx_fifo_chan(a) ((struct nvkm_fifo_chan *)nvxx_object(a))
#define nvxx_gr(a) ((struct nvkm_gr *)nvkm_engine(nvxx_object(a), NVDEV_ENGINE_GR))
#define nvxx_fifo(a) nvxx_device(a)->fifo
#define nvxx_gr(a) nvxx_device(a)->gr
#endif
drivers/gpu/drm/nouveau/include/nvif/ioctl.h
View file @ 3439633a
#ifndef __NVIF_IOCTL_H__
#define __NVIF_IOCTL_H__
#define NVIF_VERSION_LATEST 0x0000000000000000ULL
struct nvif_ioctl_v0 {
__u8 version;
#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
#define NVIF_IOCTL_V0_OWNER_ANY 0xff
__u8 owner;
#define NVIF_IOCTL_V0_NOP 0x00
#define NVIF_IOCTL_V0_SCLASS 0x01
#define NVIF_IOCTL_V0_NEW 0x02
......@@ -20,17 +19,20 @@ struct nvif_ioctl_v0 {
#define NVIF_IOCTL_V0_NTFY_GET 0x0b
#define NVIF_IOCTL_V0_NTFY_PUT 0x0c
__u8 type;
__u8 path_nr;
__u8 pad02[4];
#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
#define NVIF_IOCTL_V0_OWNER_ANY 0xff
__u8 owner;
#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
__u8 pad04[3];
__u8 route;
__u64 token;
__u32 path[8]; /* in reverse */
__u64 object;
__u8 data[]; /* ioctl data (below) */
};
struct nvif_ioctl_nop {
struct nvif_ioctl_nop_v0 {
__u64 version;
};
struct nvif_ioctl_sclass_v0 {
......@@ -38,7 +40,11 @@ struct nvif_ioctl_sclass_v0 {
__u8 version;
__u8 count;
__u8 pad02[6];
__u32 oclass[];
struct nvif_ioctl_sclass_oclass_v0 {
__s32 oclass;
__s16 minver;
__s16 maxver;
} oclass[];
};
struct nvif_ioctl_new_v0 {
......@@ -47,11 +53,17 @@ struct nvif_ioctl_new_v0 {
__u8 pad01[6];
__u8 route;
__u64 token;
__u64 object;
__u32 handle;
/* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_IOCTL_NEW_V0_PERFCTR 0x0000ffff
#define NVIF_IOCTL_NEW_V0_CONTROL 0x0000fffe
__u32 oclass;
#define NVIF_IOCTL_NEW_V0_CONTROL -1
#define NVIF_IOCTL_NEW_V0_PERFMON -2
#define NVIF_IOCTL_NEW_V0_PERFDOM -3
#define NVIF_IOCTL_NEW_V0_SW_NV04 -4
#define NVIF_IOCTL_NEW_V0_SW_NV10 -5
#define NVIF_IOCTL_NEW_V0_SW_NV50 -6
#define NVIF_IOCTL_NEW_V0_SW_GF100 -7
__s32 oclass;
__u8 data[]; /* class data (class.h) */
};
......
drivers/gpu/drm/nouveau/include/nvif/notify.h
View file @ 3439633a
......@@ -23,17 +23,11 @@ struct nvif_notify {
struct work_struct work;
};
int nvif_notify_init(struct nvif_object *, void (*dtor)(struct nvif_notify *),
int (*func)(struct nvif_notify *), bool work, u8 type,
void *data, u32 size, u32 reply, struct nvif_notify *);
int nvif_notify_init(struct nvif_object *, int (*func)(struct nvif_notify *),
bool work, u8 type, void *data, u32 size, u32 reply,
struct nvif_notify *);
int nvif_notify_fini(struct nvif_notify *);
int nvif_notify_get(struct nvif_notify *);
int nvif_notify_put(struct nvif_notify *);
int nvif_notify(const void *, u32, const void *, u32);
int nvif_notify_new(struct nvif_object *, int (*func)(struct nvif_notify *),
bool work, u8 type, void *data, u32 size, u32 reply,
struct nvif_notify **);
void nvif_notify_ref(struct nvif_notify *, struct nvif_notify **);
#endif
drivers/gpu/drm/nouveau/include/nvif/object.h
View file @ 3439633a
......@@ -3,73 +3,73 @@
#include <nvif/os.h>
struct nvif_sclass {
s32 oclass;
int minver;
int maxver;
};
struct nvif_object {
struct nvif_object *parent;
struct nvif_object *object; /*XXX: hack for nvif_object() */
struct kref refcount;
struct nvif_client *client;
u32 handle;
u32 oclass;
void *data;
u32 size;
s32 oclass;
void *priv; /*XXX: hack */
void (*dtor)(struct nvif_object *);
struct {
void __iomem *ptr;
u32 size;
} map;
};
int nvif_object_init(struct nvif_object *, void (*dtor)(struct nvif_object *),
u32 handle, u32 oclass, void *, u32,
int nvif_object_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
struct nvif_object *);
void nvif_object_fini(struct nvif_object *);
int nvif_object_new(struct nvif_object *, u32 handle, u32 oclass,
void *, u32, struct nvif_object **);
void nvif_object_ref(struct nvif_object *, struct nvif_object **);
int nvif_object_ioctl(struct nvif_object *, void *, u32, void **);
int nvif_object_sclass(struct nvif_object *, u32 *, int);
int nvif_object_sclass_get(struct nvif_object *, struct nvif_sclass **);
void nvif_object_sclass_put(struct nvif_sclass **);
u32 nvif_object_rd(struct nvif_object *, int, u64);
void nvif_object_wr(struct nvif_object *, int, u64, u32);
int nvif_object_mthd(struct nvif_object *, u32, void *, u32);
int nvif_object_map(struct nvif_object *);
void nvif_object_unmap(struct nvif_object *);
#define nvif_handle(a) (unsigned long)(void *)(a)
#define nvif_object(a) (a)->object
#define ioread8_native ioread8
#define iowrite8_native iowrite8
#define nvif_rd(a,b,c) ({ \
struct nvif_object *_object = nvif_object(a); \
#define nvif_rd(a,f,b,c) ({ \
struct nvif_object *_object = (a); \
u32 _data; \
if (likely(_object->map.ptr)) \
_data = ioread##b##_native((u8 __iomem *)_object->map.ptr + (c)); \
_data = f((u8 __iomem *)_object->map.ptr + (c)); \
else \
_data = nvif_object_rd(_object, (b) / 8, (c)); \
_data = nvif_object_rd(_object, (b), (c)); \
_data; \
})
#define nvif_wr(a,b,c,d) ({ \
struct nvif_object *_object = nvif_object(a); \
#define nvif_wr(a,f,b,c,d) ({ \
struct nvif_object *_object = (a); \
if (likely(_object->map.ptr)) \
iowrite##b##_native((d), (u8 __iomem *)_object->map.ptr + (c)); \
f((d), (u8 __iomem *)_object->map.ptr + (c)); \
else \
nvif_object_wr(_object, (b) / 8, (c), (d)); \
nvif_object_wr(_object, (b), (c), (d)); \
})
#define nvif_rd08(a,b) ({ u8 _v = nvif_rd((a), 8, (b)); _v; })
#define nvif_rd16(a,b) ({ u16 _v = nvif_rd((a), 16, (b)); _v; })
#define nvif_rd32(a,b) ({ u32 _v = nvif_rd((a), 32, (b)); _v; })
#define nvif_wr08(a,b,c) nvif_wr((a), 8, (b), (u8)(c))
#define nvif_wr16(a,b,c) nvif_wr((a), 16, (b), (u16)(c))
#define nvif_wr32(a,b,c) nvif_wr((a), 32, (b), (u32)(c))
#define nvif_rd08(a,b) ({ ((u8)nvif_rd((a), ioread8, 1, (b))); })
#define nvif_rd16(a,b) ({ ((u16)nvif_rd((a), ioread16_native, 2, (b))); })
#define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); })
#define nvif_wr08(a,b,c) nvif_wr((a), iowrite8, 1, (b), (u8)(c))
#define nvif_wr16(a,b,c) nvif_wr((a), iowrite16_native, 2, (b), (u16)(c))
#define nvif_wr32(a,b,c) nvif_wr((a), iowrite32_native, 4, (b), (u32)(c))
#define nvif_mask(a,b,c,d) ({ \
u32 _v = nvif_rd32(nvif_object(a), (b)); \
nvif_wr32(nvif_object(a), (b), (_v & ~(c)) | (d)); \
_v; \
struct nvif_object *__object = (a); \
u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
nvif_wr32(__object, _addr, (_data & ~(c)) | (d)); \
_data; \
})
#define nvif_mthd(a,b,c,d) nvif_object_mthd(nvif_object(a), (b), (c), (d))
#define nvif_mthd(a,b,c,d) nvif_object_mthd((a), (b), (c), (d))
/*XXX*/
#include <core/object.h>
#define nvxx_object(a) ((struct nvkm_object *)nvif_object(a)->priv)
#define nvxx_object(a) ({ \
struct nvif_object *_object = (a); \
(struct nvkm_object *)_object->priv; \
})
#endif
drivers/gpu/drm/nouveau/include/nvif/os.h
View file @ 3439633a
......@@ -24,9 +24,15 @@
#include <linux/power_supply.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
#include <linux/agp_backend.h>
#include <linux/reset.h>
#include <linux/iommu.h>
#include <asm/unaligned.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h>
#ifndef ioread32_native
#ifdef __BIG_ENDIAN
#define ioread16_native ioread16be
......@@ -40,5 +46,4 @@
#define iowrite32_native iowrite32
#endif /* def __BIG_ENDIAN else */
#endif /* !ioread32_native */
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/client.h
View file @ 3439633a
#ifndef __NVKM_CLIENT_H__
#define __NVKM_CLIENT_H__
#include <core/namedb.h>
#include <core/object.h>
struct nvkm_client {
struct nvkm_namedb namedb;
struct nvkm_handle *root;
struct nvkm_object *device;
struct nvkm_object object;
char name[32];
u64 device;
u32 debug;
struct nvkm_vm *vm;
struct nvkm_client_notify *notify[16];
struct rb_root objroot;
struct rb_root dmaroot;
bool super;
void *data;
int (*ntfy)(const void *, u32, const void *, u32);
struct nvkm_client_notify *notify[16];
struct nvkm_vm *vm;
};
static inline struct nvkm_client *
nv_client(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS)))
nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj));
#endif
return obj;
}
static inline struct nvkm_client *
nvkm_client(void *obj)
{
struct nvkm_object *client = nv_object(obj);
while (client && !(nv_iclass(client, NV_CLIENT_CLASS)))
client = client->parent;
return (void *)client;
}
#define nvkm_client_create(n,c,oc,od,d) \
nvkm_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d)
int nvkm_client_create_(const char *name, u64 device, const char *cfg,
const char *dbg, int, void **);
#define nvkm_client_destroy(p) \
nvkm_namedb_destroy(&(p)->base)
bool nvkm_client_insert(struct nvkm_client *, struct nvkm_object *);
void nvkm_client_remove(struct nvkm_client *, struct nvkm_object *);
struct nvkm_object *nvkm_client_search(struct nvkm_client *, u64 object);
int nvkm_client_new(const char *name, u64 device, const char *cfg,
const char *dbg, struct nvkm_client **);
void nvkm_client_del(struct nvkm_client **);
int nvkm_client_init(struct nvkm_client *);
int nvkm_client_fini(struct nvkm_client *, bool suspend);
const char *nvkm_client_name(void *obj);
int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *,
void *data, u32 size);
int nvkm_client_notify_del(struct nvkm_client *, int index);
int nvkm_client_notify_get(struct nvkm_client *, int index);
int nvkm_client_notify_put(struct nvkm_client *, int index);
/* logging for client-facing objects */
#define nvif_printk(o,l,p,f,a...) do { \
struct nvkm_object *_object = (o); \
struct nvkm_client *_client = _object->client; \
if (_client->debug >= NV_DBG_##l) \
printk(KERN_##p "nouveau: %s:%08x:%08x: "f, _client->name, \
_object->handle, _object->oclass, ##a); \
} while(0)
#define nvif_fatal(o,f,a...) nvif_printk((o), FATAL, CRIT, f, ##a)
#define nvif_error(o,f,a...) nvif_printk((o), ERROR, ERR, f, ##a)
#define nvif_debug(o,f,a...) nvif_printk((o), DEBUG, INFO, f, ##a)
#define nvif_trace(o,f,a...) nvif_printk((o), TRACE, INFO, f, ##a)
#define nvif_info(o,f,a...) nvif_printk((o), INFO, INFO, f, ##a)
#define nvif_ioctl(o,f,a...) nvif_trace((o), "ioctl: "f, ##a)
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
View file @ 3439633a
#ifndef __NVKM_DEBUG_H__
#define __NVKM_DEBUG_H__
extern int nv_info_debug_level;
#define NV_DBG_FATAL 0
#define NV_DBG_ERROR 1
#define NV_DBG_WARN 2
#define NV_DBG_INFO nv_info_debug_level
#define NV_DBG_INFO 3
#define NV_DBG_DEBUG 4
#define NV_DBG_TRACE 5
#define NV_DBG_PARANOIA 6
#define NV_DBG_SPAM 7
#define NV_DBG_INFO_NORMAL 3
#define NV_DBG_INFO_SILENT NV_DBG_DEBUG
#define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file @ 3439633a
#ifndef __NVKM_DEVICE_H__
#define __NVKM_DEVICE_H__
#include <core/engine.h>
#include <core/event.h>
#include <core/object.h>
enum nvkm_devidx {
NVKM_SUBDEV_PCI,
NVKM_SUBDEV_VBIOS,
NVKM_SUBDEV_DEVINIT,
NVKM_SUBDEV_IBUS,
NVKM_SUBDEV_GPIO,
NVKM_SUBDEV_I2C,
NVKM_SUBDEV_FUSE,
NVKM_SUBDEV_MXM,
NVKM_SUBDEV_MC,
NVKM_SUBDEV_BUS,
NVKM_SUBDEV_TIMER,
NVKM_SUBDEV_FB,
NVKM_SUBDEV_LTC,
NVKM_SUBDEV_INSTMEM,
NVKM_SUBDEV_MMU,
NVKM_SUBDEV_BAR,
NVKM_SUBDEV_PMU,
NVKM_SUBDEV_VOLT,
NVKM_SUBDEV_THERM,
NVKM_SUBDEV_CLK,
NVKM_ENGINE_DMAOBJ,
NVKM_ENGINE_IFB,
NVKM_ENGINE_FIFO,
NVKM_ENGINE_SW,
NVKM_ENGINE_GR,
NVKM_ENGINE_MPEG,
NVKM_ENGINE_ME,
NVKM_ENGINE_VP,
NVKM_ENGINE_CIPHER,
NVKM_ENGINE_BSP,
NVKM_ENGINE_MSPPP,
NVKM_ENGINE_CE0,
NVKM_ENGINE_CE1,
NVKM_ENGINE_CE2,
NVKM_ENGINE_VIC,
NVKM_ENGINE_MSENC,
NVKM_ENGINE_DISP,
NVKM_ENGINE_PM,
NVKM_ENGINE_MSVLD,
NVKM_ENGINE_SEC,
NVKM_ENGINE_MSPDEC,
NVKM_SUBDEV_NR
};
enum nvkm_device_type {
NVKM_DEVICE_PCI,
NVKM_DEVICE_AGP,
NVKM_DEVICE_PCIE,
NVKM_DEVICE_TEGRA,
};
struct nvkm_device {
struct nvkm_engine engine;
const struct nvkm_device_func *func;
const struct nvkm_device_quirk *quirk;
struct device *dev;
enum nvkm_device_type type;
u64 handle;
const char *name;
const char *cfgopt;
const char *dbgopt;
struct list_head head;
struct mutex mutex;
int refcount;
struct pci_dev *pdev;
struct platform_device *platformdev;
u64 handle;
void __iomem *pri;
struct nvkm_event event;
const char *cfgopt;
const char *dbgopt;
const char *name;
const char *cname;
u64 disable_mask;
u32 debug;
const struct nvkm_device_chip *chip;
enum {
NV_04 = 0x04,
NV_10 = 0x10,
......@@ -35,67 +95,157 @@ struct nvkm_device {
u8 chiprev;
u32 crystal;
struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
struct {
struct notifier_block nb;
} acpi;
struct nvkm_bar *bar;
struct nvkm_bios *bios;
struct nvkm_bus *bus;
struct nvkm_clk *clk;
struct nvkm_devinit *devinit;
struct nvkm_fb *fb;
struct nvkm_fuse *fuse;
struct nvkm_gpio *gpio;
struct nvkm_i2c *i2c;
struct nvkm_subdev *ibus;
struct nvkm_instmem *imem;
struct nvkm_ltc *ltc;
struct nvkm_mc *mc;
struct nvkm_mmu *mmu;
struct nvkm_subdev *mxm;
struct nvkm_pci *pci;
struct nvkm_pmu *pmu;
struct nvkm_therm *therm;
struct nvkm_timer *timer;
struct nvkm_volt *volt;
struct nvkm_engine *bsp;
struct nvkm_engine *ce[3];
struct nvkm_engine *cipher;
struct nvkm_disp *disp;
struct nvkm_dma *dma;
struct nvkm_fifo *fifo;
struct nvkm_gr *gr;
struct nvkm_engine *ifb;
struct nvkm_engine *me;
struct nvkm_engine *mpeg;
struct nvkm_engine *msenc;
struct nvkm_engine *mspdec;
struct nvkm_engine *msppp;
struct nvkm_engine *msvld;
struct nvkm_pm *pm;
struct nvkm_engine *sec;
struct nvkm_sw *sw;
struct nvkm_engine *vic;
struct nvkm_engine *vp;
};
struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);
struct nvkm_device_func {
struct nvkm_device_pci *(*pci)(struct nvkm_device *);
struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
void *(*dtor)(struct nvkm_device *);
int (*preinit)(struct nvkm_device *);
int (*init)(struct nvkm_device *);
void (*fini)(struct nvkm_device *, bool suspend);
resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar);
resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar);
bool cpu_coherent;
};
struct nvkm_device_quirk {
u8 tv_pin_mask;
u8 tv_gpio;
bool War00C800_0;
};
struct nvkm_device_chip {
const char *name;
int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **);
int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
int (*devinit)(struct nvkm_device *, int idx, struct nvkm_devinit **);
int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);
int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **);
int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **);
int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **);
int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **);
int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **);
int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **);
int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **);
int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
int (*pci )(struct nvkm_device *, int idx, struct nvkm_pci **);
int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);
int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **);
int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **);
int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **);
int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*ce[3] )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **);
int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
};
struct nvkm_device *nvkm_device_find(u64 name);
int nvkm_device_list(u64 *name, int size);
struct nvkm_device *nv_device(void *obj);
static inline bool
nv_device_match(struct nvkm_object *object, u16 dev, u16 ven, u16 sub)
{
struct nvkm_device *device = nv_device(object);
return device->pdev->device == dev &&
device->pdev->subsystem_vendor == ven &&
device->pdev->subsystem_device == sub;
}
static inline bool
nv_device_is_pci(struct nvkm_device *device)
{
return device->pdev != NULL;
}
static inline bool
nv_device_is_cpu_coherent(struct nvkm_device *device)
{
return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
}
static inline struct device *
nv_device_base(struct nvkm_device *device)
{
return nv_device_is_pci(device) ? &device->pdev->dev :
&device->platformdev->dev;
}
resource_size_t
nv_device_resource_start(struct nvkm_device *device, unsigned int bar);
resource_size_t
nv_device_resource_len(struct nvkm_device *device, unsigned int bar);
int
nv_device_get_irq(struct nvkm_device *device, bool stall);
struct platform_device;
enum nv_bus_type {
NVKM_BUS_PCI,
NVKM_BUS_PLATFORM,
/* privileged register interface accessor macros */
#define nvkm_rd08(d,a) ioread8((d)->pri + (a))
#define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
#define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
#define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
#define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
#define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
#define nvkm_mask(d,a,m,v) ({ \
struct nvkm_device *_device = (d); \
u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
_temp; \
})
void nvkm_device_del(struct nvkm_device **);
struct nvkm_device_oclass {
int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *,
void *data, u32 size, struct nvkm_object **);
struct nvkm_sclass base;
};
#define nvkm_device_create(p,t,n,s,c,d,u) \
nvkm_device_create_((void *)(p), (t), (n), (s), (c), (d), \
sizeof(**u), (void **)u)
int nvkm_device_create_(void *, enum nv_bus_type type, u64 name,
const char *sname, const char *cfg, const char *dbg,
int, void **);
extern const struct nvkm_sclass nvkm_udevice_sclass;
/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do { \
struct nvkm_device *_device = (d); \
if (_device->debug >= (l)) \
dev_##p(_device->dev, f, ##a); \
} while(0)
#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
#define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a)
#define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a)
#define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a)
#define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a)
#define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a)
#define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a)
#define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a)
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_DEVIDX_H__
#define __NVKM_DEVIDX_H__
enum nvkm_devidx {
NVDEV_ENGINE_DEVICE,
NVDEV_SUBDEV_VBIOS,
/* All subdevs from DEVINIT to DEVINIT_LAST will be created before
* *any* of them are initialised. This subdev category is used
* for any subdevs that the VBIOS init table parsing may call out
* to during POST.
*/
NVDEV_SUBDEV_DEVINIT,
NVDEV_SUBDEV_IBUS,
NVDEV_SUBDEV_GPIO,
NVDEV_SUBDEV_I2C,
NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
/* This grouping of subdevs are initialised right after they've
* been created, and are allowed to assume any subdevs in the
* list above them exist and have been initialised.
*/
NVDEV_SUBDEV_FUSE,
NVDEV_SUBDEV_MXM,
NVDEV_SUBDEV_MC,
NVDEV_SUBDEV_BUS,
NVDEV_SUBDEV_TIMER,
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTC,
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_MMU,
NVDEV_SUBDEV_BAR,
NVDEV_SUBDEV_PMU,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLK,
NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_IFB,
NVDEV_ENGINE_FIFO,
NVDEV_ENGINE_SW,
NVDEV_ENGINE_GR,
NVDEV_ENGINE_MPEG,
NVDEV_ENGINE_ME,
NVDEV_ENGINE_VP,
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_MSPPP,
NVDEV_ENGINE_CE0,
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_MSENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
NVDEV_ENGINE_MSPDEC,
NVDEV_SUBDEV_NR,
};
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_ENGCTX_H__
#define __NVKM_ENGCTX_H__
#include <core/gpuobj.h>
#include <subdev/mmu.h>
#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
struct nvkm_engctx {
struct nvkm_gpuobj gpuobj;
struct nvkm_vma vma;
struct list_head head;
unsigned long save;
u64 addr;
};
static inline struct nvkm_engctx *
nv_engctx(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_ENGCTX_CLASS)))
nv_assert("BAD CAST -> NvEngCtx, %08x", nv_hclass(obj));
#endif
return obj;
}
#define nvkm_engctx_create(p,e,c,g,s,a,f,d) \
nvkm_engctx_create_((p), (e), (c), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
int nvkm_engctx_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, struct nvkm_object *,
u32 size, u32 align, u32 flags,
int length, void **data);
void nvkm_engctx_destroy(struct nvkm_engctx *);
int nvkm_engctx_init(struct nvkm_engctx *);
int nvkm_engctx_fini(struct nvkm_engctx *, bool suspend);
int _nvkm_engctx_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void _nvkm_engctx_dtor(struct nvkm_object *);
int _nvkm_engctx_init(struct nvkm_object *);
int _nvkm_engctx_fini(struct nvkm_object *, bool suspend);
#define _nvkm_engctx_rd32 _nvkm_gpuobj_rd32
#define _nvkm_engctx_wr32 _nvkm_gpuobj_wr32
struct nvkm_object *nvkm_engctx_get(struct nvkm_engine *, u64 addr);
void nvkm_engctx_put(struct nvkm_object *);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View file @ 3439633a
#ifndef __NVKM_ENGINE_H__
#define __NVKM_ENGINE_H__
#define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev)
#include <core/subdev.h>
#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng))
#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var))
struct nvkm_fifo_chan;
struct nvkm_fb_tile;
struct nvkm_engine {
const struct nvkm_engine_func *func;
struct nvkm_subdev subdev;
struct nvkm_oclass *cclass;
struct nvkm_oclass *sclass;
struct list_head contexts;
spinlock_t lock;
void (*tile_prog)(struct nvkm_engine *, int region);
int (*tlb_flush)(struct nvkm_engine *);
int usecount;
};
static inline struct nvkm_engine *
nv_engine(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_ENGINE_CLASS)))
nv_assert("BAD CAST -> NvEngine, %08x", nv_hclass(obj));
#endif
return obj;
}
static inline int
nv_engidx(struct nvkm_engine *engine)
{
return nv_subidx(&engine->subdev);
}
struct nvkm_engine *nvkm_engine(void *obj, int idx);
#define nvkm_engine_create(p,e,c,d,i,f,r) \
nvkm_engine_create_((p), (e), (c), (d), (i), (f), \
sizeof(**r),(void **)r)
#define nvkm_engine_destroy(p) \
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_engine_init(p) \
nvkm_subdev_init(&(p)->subdev)
#define nvkm_engine_fini(p,s) \
nvkm_subdev_fini(&(p)->subdev, (s))
int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, bool, const char *,
const char *, int, void **);
struct nvkm_engine_func {
void *(*dtor)(struct nvkm_engine *);
int (*oneinit)(struct nvkm_engine *);
int (*init)(struct nvkm_engine *);
int (*fini)(struct nvkm_engine *, bool suspend);
void (*intr)(struct nvkm_engine *);
void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *);
struct {
int (*sclass)(struct nvkm_oclass *, int index,
const struct nvkm_device_oclass **);
} base;
struct {
int (*cclass)(struct nvkm_fifo_chan *,
const struct nvkm_oclass *,
struct nvkm_object **);
int (*sclass)(struct nvkm_oclass *, int index);
} fifo;
const struct nvkm_object_func *cclass;
struct nvkm_sclass sclass[];
};
#define _nvkm_engine_dtor _nvkm_subdev_dtor
#define _nvkm_engine_init _nvkm_subdev_init
#define _nvkm_engine_fini _nvkm_subdev_fini
int nvkm_engine_ctor(const struct nvkm_engine_func *, struct nvkm_device *,
int index, u32 pmc_enable, bool enable,
struct nvkm_engine *);
int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *,
int index, u32 pmc_enable, bool enable,
struct nvkm_engine **);
struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *);
void nvkm_engine_unref(struct nvkm_engine **);
void nvkm_engine_tile(struct nvkm_engine *, int region);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
View file @ 3439633a
......@@ -10,12 +10,11 @@ struct nvkm_enum {
};
const struct nvkm_enum *nvkm_enum_find(const struct nvkm_enum *, u32 value);
const struct nvkm_enum *nvkm_enum_print(const struct nvkm_enum *, u32 value);
struct nvkm_bitfield {
u32 mask;
const char *name;
};
void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value);
void nvkm_snprintbf(char *, int, const struct nvkm_bitfield *, u32 value);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
View file @ 3439633a
#ifndef __NVKM_GPUOBJ_H__
#define __NVKM_GPUOBJ_H__
#include <core/object.h>
#include <core/memory.h>
#include <core/mm.h>
struct nvkm_vma;
struct nvkm_vm;
#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001
#define NVOBJ_FLAG_ZERO_FREE 0x00000002
#define NVOBJ_FLAG_HEAP 0x00000004
struct nvkm_gpuobj {
struct nvkm_object object;
struct nvkm_object *parent;
const struct nvkm_gpuobj_func *func;
struct nvkm_gpuobj *parent;
struct nvkm_memory *memory;
struct nvkm_mm_node *node;
struct nvkm_mm heap;
u32 flags;
u64 addr;
u32 size;
};
struct nvkm_mm heap;
static inline struct nvkm_gpuobj *
nv_gpuobj(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_GPUOBJ_CLASS)))
nv_assert("BAD CAST -> NvGpuObj, %08x", nv_hclass(obj));
#endif
return obj;
}
void __iomem *map;
};
#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \
nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
#define nvkm_gpuobj_init(p) nvkm_object_init(&(p)->object)
#define nvkm_gpuobj_fini(p,s) nvkm_object_fini(&(p)->object, (s))
int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32 pclass,
struct nvkm_object *, u32 size, u32 align,
u32 flags, int length, void **);
void nvkm_gpuobj_destroy(struct nvkm_gpuobj *);
struct nvkm_gpuobj_func {
void *(*acquire)(struct nvkm_gpuobj *);
void (*release)(struct nvkm_gpuobj *);
u32 (*rd32)(struct nvkm_gpuobj *, u32 offset);
void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data);
};
int nvkm_gpuobj_new(struct nvkm_object *, struct nvkm_object *, u32 size,
u32 align, u32 flags, struct nvkm_gpuobj **);
int nvkm_gpuobj_dup(struct nvkm_object *, struct nvkm_gpuobj *,
struct nvkm_gpuobj **);
int nvkm_gpuobj_map(struct nvkm_gpuobj *, u32 acc, struct nvkm_vma *);
int nvkm_gpuobj_map_vm(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero,
struct nvkm_gpuobj *parent, struct nvkm_gpuobj **);
void nvkm_gpuobj_del(struct nvkm_gpuobj **);
int nvkm_gpuobj_wrap(struct nvkm_memory *, struct nvkm_gpuobj **);
int nvkm_gpuobj_map(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
struct nvkm_vma *);
void nvkm_gpuobj_unmap(struct nvkm_vma *);
static inline void
nvkm_gpuobj_ref(struct nvkm_gpuobj *obj, struct nvkm_gpuobj **ref)
{
nvkm_object_ref(&obj->object, (struct nvkm_object **)ref);
}
void _nvkm_gpuobj_dtor(struct nvkm_object *);
int _nvkm_gpuobj_init(struct nvkm_object *);
int _nvkm_gpuobj_fini(struct nvkm_object *, bool);
u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64);
void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/handle.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_HANDLE_H__
#define __NVKM_HANDLE_H__
#include <core/os.h>
struct nvkm_object;
struct nvkm_handle {
struct nvkm_namedb *namedb;
struct list_head node;
struct list_head head;
struct list_head tree;
u32 name;
u32 priv;
u8 route;
u64 token;
struct nvkm_handle *parent;
struct nvkm_object *object;
};
int nvkm_handle_create(struct nvkm_object *, u32 parent, u32 handle,
struct nvkm_object *, struct nvkm_handle **);
void nvkm_handle_destroy(struct nvkm_handle *);
int nvkm_handle_init(struct nvkm_handle *);
int nvkm_handle_fini(struct nvkm_handle *, bool suspend);
struct nvkm_object *nvkm_handle_ref(struct nvkm_object *, u32 name);
struct nvkm_handle *nvkm_handle_get_class(struct nvkm_object *, u16);
struct nvkm_handle *nvkm_handle_get_vinst(struct nvkm_object *, u64);
struct nvkm_handle *nvkm_handle_get_cinst(struct nvkm_object *, u32);
void nvkm_handle_put(struct nvkm_handle *);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/memory.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_MEMORY_H__
#define __NVKM_MEMORY_H__
#include <core/os.h>
struct nvkm_device;
struct nvkm_vma;
struct nvkm_vm;
enum nvkm_memory_target {
NVKM_MEM_TARGET_INST,
NVKM_MEM_TARGET_VRAM,
NVKM_MEM_TARGET_HOST,
};
struct nvkm_memory {
const struct nvkm_memory_func *func;
};
struct nvkm_memory_func {
void *(*dtor)(struct nvkm_memory *);
enum nvkm_memory_target (*target)(struct nvkm_memory *);
u64 (*addr)(struct nvkm_memory *);
u64 (*size)(struct nvkm_memory *);
void (*boot)(struct nvkm_memory *, struct nvkm_vm *);
void __iomem *(*acquire)(struct nvkm_memory *);
void (*release)(struct nvkm_memory *);
u32 (*rd32)(struct nvkm_memory *, u64 offset);
void (*wr32)(struct nvkm_memory *, u64 offset, u32 data);
void (*map)(struct nvkm_memory *, struct nvkm_vma *, u64 offset);
};
void nvkm_memory_ctor(const struct nvkm_memory_func *, struct nvkm_memory *);
int nvkm_memory_new(struct nvkm_device *, enum nvkm_memory_target,
u64 size, u32 align, bool zero, struct nvkm_memory **);
void nvkm_memory_del(struct nvkm_memory **);
#define nvkm_memory_target(p) (p)->func->target(p)
#define nvkm_memory_addr(p) (p)->func->addr(p)
#define nvkm_memory_size(p) (p)->func->size(p)
#define nvkm_memory_boot(p,v) (p)->func->boot((p),(v))
#define nvkm_memory_map(p,v,o) (p)->func->map((p),(v),(o))
/* accessor macros - kmap()/done() must bracket use of the other accessor
* macros to guarantee correct behaviour across all chipsets
*/
#define nvkm_kmap(o) (o)->func->acquire(o)
#define nvkm_ro32(o,a) (o)->func->rd32((o), (a))
#define nvkm_wo32(o,a,d) (o)->func->wr32((o), (a), (d))
#define nvkm_mo32(o,a,m,d) ({ \
u32 _addr = (a), _data = nvkm_ro32((o), _addr); \
nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
_data; \
})
#define nvkm_done(o) (o)->func->release(o)
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
View file @ 3439633a
......@@ -27,7 +27,7 @@ struct nvkm_mm {
static inline bool
nvkm_mm_initialised(struct nvkm_mm *mm)
{
return mm->block_size != 0;
return mm->heap_nodes;
}
int nvkm_mm_init(struct nvkm_mm *, u32 offset, u32 length, u32 block);
......@@ -37,4 +37,5 @@ int nvkm_mm_head(struct nvkm_mm *, u8 heap, u8 type, u32 size_max,
int nvkm_mm_tail(struct nvkm_mm *, u8 heap, u8 type, u32 size_max,
u32 size_min, u32 align, struct nvkm_mm_node **);
void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **);
void nvkm_mm_dump(struct nvkm_mm *, const char *);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_NAMEDB_H__
#define __NVKM_NAMEDB_H__
#include <core/parent.h>
struct nvkm_handle;
struct nvkm_namedb {
struct nvkm_parent parent;
rwlock_t lock;
struct list_head list;
};
static inline struct nvkm_namedb *
nv_namedb(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_NAMEDB_CLASS)))
nv_assert("BAD CAST -> NvNameDB, %08x", nv_hclass(obj));
#endif
return obj;
}
#define nvkm_namedb_create(p,e,c,v,s,m,d) \
nvkm_namedb_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
#define nvkm_namedb_init(p) \
nvkm_parent_init(&(p)->parent)
#define nvkm_namedb_fini(p,s) \
nvkm_parent_fini(&(p)->parent, (s))
#define nvkm_namedb_destroy(p) \
nvkm_parent_destroy(&(p)->parent)
int nvkm_namedb_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32 pclass,
struct nvkm_oclass *, u64 engcls,
int size, void **);
int _nvkm_namedb_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
#define _nvkm_namedb_dtor _nvkm_parent_dtor
#define _nvkm_namedb_init _nvkm_parent_init
#define _nvkm_namedb_fini _nvkm_parent_fini
int nvkm_namedb_insert(struct nvkm_namedb *, u32 name, struct nvkm_object *,
struct nvkm_handle *);
void nvkm_namedb_remove(struct nvkm_handle *);
struct nvkm_handle *nvkm_namedb_get(struct nvkm_namedb *, u32);
struct nvkm_handle *nvkm_namedb_get_class(struct nvkm_namedb *, u16);
struct nvkm_handle *nvkm_namedb_get_vinst(struct nvkm_namedb *, u64);
struct nvkm_handle *nvkm_namedb_get_cinst(struct nvkm_namedb *, u32);
void nvkm_namedb_put(struct nvkm_handle *);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
View file @ 3439633a
#ifndef __NVKM_OBJECT_H__
#define __NVKM_OBJECT_H__
#include <core/os.h>
#include <core/printk.h>
#define NV_PARENT_CLASS 0x80000000
#define NV_NAMEDB_CLASS 0x40000000
#define NV_CLIENT_CLASS 0x20000000
#define NV_SUBDEV_CLASS 0x10000000
#define NV_ENGINE_CLASS 0x08000000
#define NV_MEMOBJ_CLASS 0x04000000
#define NV_GPUOBJ_CLASS 0x02000000
#define NV_ENGCTX_CLASS 0x01000000
#define NV_OBJECT_CLASS 0x0000ffff
#include <core/debug.h>
struct nvkm_event;
struct nvkm_gpuobj;
struct nvkm_oclass;
struct nvkm_object {
struct nvkm_oclass *oclass;
struct nvkm_object *parent;
const struct nvkm_object_func *func;
struct nvkm_client *client;
struct nvkm_engine *engine;
atomic_t refcount;
atomic_t usecount;
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
#define NVKM_OBJECT_MAGIC 0x75ef0bad
struct list_head list;
u32 _magic;
#endif
};
static inline struct nvkm_object *
nv_object(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (likely(obj)) {
struct nvkm_object *object = obj;
if (unlikely(object->_magic != NVKM_OBJECT_MAGIC))
nv_assert("BAD CAST -> NvObject, invalid magic");
}
#endif
return obj;
}
#define nvkm_object_create(p,e,c,s,d) \
nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32, int size, void **);
void nvkm_object_destroy(struct nvkm_object *);
int nvkm_object_init(struct nvkm_object *);
int nvkm_object_fini(struct nvkm_object *, bool suspend);
int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
extern struct nvkm_ofuncs nvkm_object_ofuncs;
/* Don't allocate dynamically, because lockdep needs lock_class_keys to be in
* ".data". */
struct nvkm_oclass {
s32 oclass;
u32 handle;
struct nvkm_ofuncs * const ofuncs;
struct nvkm_omthds * const omthds;
struct lock_class_key lock_class_key;
};
#define nv_oclass(o) nv_object(o)->oclass
#define nv_hclass(o) nv_oclass(o)->handle
#define nv_iclass(o,i) (nv_hclass(o) & (i))
#define nv_mclass(o) nv_iclass(o, NV_OBJECT_CLASS)
static inline struct nvkm_object *
nv_pclass(struct nvkm_object *parent, u32 oclass)
{
while (parent && !nv_iclass(parent, oclass))
parent = parent->parent;
return parent;
}
struct nvkm_omthds {
u32 start;
u32 limit;
int (*call)(struct nvkm_object *, u32, void *, u32);
struct list_head head;
struct list_head tree;
u8 route;
u64 token;
u64 object;
struct rb_node node;
};
struct nvkm_event;
struct nvkm_ofuncs {
int (*ctor)(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
void (*dtor)(struct nvkm_object *);
struct nvkm_object_func {
void *(*dtor)(struct nvkm_object *);
int (*init)(struct nvkm_object *);
int (*fini)(struct nvkm_object *, bool suspend);
int (*mthd)(struct nvkm_object *, u32, void *, u32);
int (*ntfy)(struct nvkm_object *, u32, struct nvkm_event **);
int (* map)(struct nvkm_object *, u64 *, u32 *);
u8 (*rd08)(struct nvkm_object *, u64 offset);
u16 (*rd16)(struct nvkm_object *, u64 offset);
u32 (*rd32)(struct nvkm_object *, u64 offset);
void (*wr08)(struct nvkm_object *, u64 offset, u8 data);
void (*wr16)(struct nvkm_object *, u64 offset, u16 data);
void (*wr32)(struct nvkm_object *, u64 offset, u32 data);
int (*mthd)(struct nvkm_object *, u32 mthd, void *data, u32 size);
int (*ntfy)(struct nvkm_object *, u32 mthd, struct nvkm_event **);
int (*map)(struct nvkm_object *, u64 *addr, u32 *size);
int (*rd08)(struct nvkm_object *, u64 addr, u8 *data);
int (*rd16)(struct nvkm_object *, u64 addr, u16 *data);
int (*rd32)(struct nvkm_object *, u64 addr, u32 *data);
int (*wr08)(struct nvkm_object *, u64 addr, u8 data);
int (*wr16)(struct nvkm_object *, u64 addr, u16 data);
int (*wr32)(struct nvkm_object *, u64 addr, u32 data);
int (*bind)(struct nvkm_object *, struct nvkm_gpuobj *, int align,
struct nvkm_gpuobj **);
int (*sclass)(struct nvkm_object *, int index, struct nvkm_oclass *);
};
static inline struct nvkm_ofuncs *
nv_ofuncs(void *obj)
{
return nv_oclass(obj)->ofuncs;
}
int nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
void nvkm_object_ctor(const struct nvkm_object_func *,
const struct nvkm_oclass *, struct nvkm_object *);
int nvkm_object_new_(const struct nvkm_object_func *,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **);
int nvkm_object_inc(struct nvkm_object *);
int nvkm_object_dec(struct nvkm_object *, bool suspend);
void nvkm_object_debug(void);
static inline int
nv_exec(void *obj, u32 mthd, void *data, u32 size)
{
struct nvkm_omthds *method = nv_oclass(obj)->omthds;
while (method && method->call) {
if (mthd >= method->start && mthd <= method->limit)
return method->call(obj, mthd, data, size);
method++;
}
return -EINVAL;
}
static inline int
nv_call(void *obj, u32 mthd, u32 data)
{
return nv_exec(obj, mthd, &data, sizeof(data));
}
static inline u8
nv_ro08(void *obj, u64 addr)
{
u8 data = nv_ofuncs(obj)->rd08(obj, addr);
nv_spam(obj, "nv_ro08 0x%08llx 0x%02x\n", addr, data);
return data;
}
static inline u16
nv_ro16(void *obj, u64 addr)
{
u16 data = nv_ofuncs(obj)->rd16(obj, addr);
nv_spam(obj, "nv_ro16 0x%08llx 0x%04x\n", addr, data);
return data;
}
static inline u32
nv_ro32(void *obj, u64 addr)
{
u32 data = nv_ofuncs(obj)->rd32(obj, addr);
nv_spam(obj, "nv_ro32 0x%08llx 0x%08x\n", addr, data);
return data;
}
static inline void
nv_wo08(void *obj, u64 addr, u8 data)
{
nv_spam(obj, "nv_wo08 0x%08llx 0x%02x\n", addr, data);
nv_ofuncs(obj)->wr08(obj, addr, data);
}
static inline void
nv_wo16(void *obj, u64 addr, u16 data)
{
nv_spam(obj, "nv_wo16 0x%08llx 0x%04x\n", addr, data);
nv_ofuncs(obj)->wr16(obj, addr, data);
}
static inline void
nv_wo32(void *obj, u64 addr, u32 data)
{
nv_spam(obj, "nv_wo32 0x%08llx 0x%08x\n", addr, data);
nv_ofuncs(obj)->wr32(obj, addr, data);
}
static inline u32
nv_mo32(void *obj, u64 addr, u32 mask, u32 data)
{
u32 temp = nv_ro32(obj, addr);
nv_wo32(obj, addr, (temp & ~mask) | data);
return temp;
}
static inline int
nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
{
unsigned char c1, c2;
int nvkm_object_new(const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
void nvkm_object_del(struct nvkm_object **);
void *nvkm_object_dtor(struct nvkm_object *);
int nvkm_object_init(struct nvkm_object *);
int nvkm_object_fini(struct nvkm_object *, bool suspend);
int nvkm_object_mthd(struct nvkm_object *, u32 mthd, void *data, u32 size);
int nvkm_object_ntfy(struct nvkm_object *, u32 mthd, struct nvkm_event **);
int nvkm_object_map(struct nvkm_object *, u64 *addr, u32 *size);
int nvkm_object_rd08(struct nvkm_object *, u64 addr, u8 *data);
int nvkm_object_rd16(struct nvkm_object *, u64 addr, u16 *data);
int nvkm_object_rd32(struct nvkm_object *, u64 addr, u32 *data);
int nvkm_object_wr08(struct nvkm_object *, u64 addr, u8 data);
int nvkm_object_wr16(struct nvkm_object *, u64 addr, u16 data);
int nvkm_object_wr32(struct nvkm_object *, u64 addr, u32 data);
int nvkm_object_bind(struct nvkm_object *, struct nvkm_gpuobj *, int align,
struct nvkm_gpuobj **);
struct nvkm_sclass {
int minver;
int maxver;
s32 oclass;
const struct nvkm_object_func *func;
int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
};
while (len--) {
c1 = nv_ro08(obj, addr++);
c2 = *(str++);
if (c1 != c2)
return c1 - c2;
}
return 0;
}
struct nvkm_oclass {
int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
struct nvkm_sclass base;
const void *priv;
const void *engn;
u32 handle;
u8 route;
u64 token;
u64 object;
struct nvkm_client *client;
struct nvkm_object *parent;
struct nvkm_engine *engine;
};
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_OPROXY_H__
#define __NVKM_OPROXY_H__
#define nvkm_oproxy(p) container_of((p), struct nvkm_oproxy, base)
#include <core/object.h>
struct nvkm_oproxy {
const struct nvkm_oproxy_func *func;
struct nvkm_object base;
struct nvkm_object *object;
};
struct nvkm_oproxy_func {
void (*dtor[2])(struct nvkm_oproxy *);
int (*init[2])(struct nvkm_oproxy *);
int (*fini[2])(struct nvkm_oproxy *, bool suspend);
};
void nvkm_oproxy_ctor(const struct nvkm_oproxy_func *,
const struct nvkm_oclass *, struct nvkm_oproxy *);
int nvkm_oproxy_new_(const struct nvkm_oproxy_func *,
const struct nvkm_oclass *, struct nvkm_oproxy **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/option.h
View file @ 3439633a
......@@ -4,6 +4,7 @@
const char *nvkm_stropt(const char *optstr, const char *opt, int *len);
bool nvkm_boolopt(const char *optstr, const char *opt, bool value);
long nvkm_longopt(const char *optstr, const char *opt, long value);
int nvkm_dbgopt(const char *optstr, const char *sub);
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
......
drivers/gpu/drm/nouveau/include/nvkm/core/parent.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_PARENT_H__
#define __NVKM_PARENT_H__
#include <core/object.h>
struct nvkm_sclass {
struct nvkm_sclass *sclass;
struct nvkm_engine *engine;
struct nvkm_oclass *oclass;
};
struct nvkm_parent {
struct nvkm_object object;
struct nvkm_sclass *sclass;
u64 engine;
int (*context_attach)(struct nvkm_object *, struct nvkm_object *);
int (*context_detach)(struct nvkm_object *, bool suspend,
struct nvkm_object *);
int (*object_attach)(struct nvkm_object *parent,
struct nvkm_object *object, u32 name);
void (*object_detach)(struct nvkm_object *parent, int cookie);
};
static inline struct nvkm_parent *
nv_parent(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!(nv_iclass(obj, NV_PARENT_CLASS))))
nv_assert("BAD CAST -> NvParent, %08x", nv_hclass(obj));
#endif
return obj;
}
#define nvkm_parent_create(p,e,c,v,s,m,d) \
nvkm_parent_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
#define nvkm_parent_init(p) \
nvkm_object_init(&(p)->object)
#define nvkm_parent_fini(p,s) \
nvkm_object_fini(&(p)->object, (s))
int nvkm_parent_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32 pclass,
struct nvkm_oclass *, u64 engcls,
int size, void **);
void nvkm_parent_destroy(struct nvkm_parent *);
void _nvkm_parent_dtor(struct nvkm_object *);
#define _nvkm_parent_init nvkm_object_init
#define _nvkm_parent_fini nvkm_object_fini
int nvkm_parent_sclass(struct nvkm_object *, u16 handle,
struct nvkm_object **pengine,
struct nvkm_oclass **poclass);
int nvkm_parent_lclass(struct nvkm_object *, u32 *, int);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/pci.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_DEVICE_PCI_H__
#define __NVKM_DEVICE_PCI_H__
#include <core/device.h>
struct nvkm_device_pci {
struct nvkm_device device;
struct pci_dev *pdev;
bool suspend;
};
int nvkm_device_pci_new(struct pci_dev *, const char *cfg, const char *dbg,
bool detect, bool mmio, u64 subdev_mask,
struct nvkm_device **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/printk.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_PRINTK_H__
#define __NVKM_PRINTK_H__
#include <core/os.h>
#include <core/debug.h>
struct nvkm_object;
void __printf(3, 4)
nv_printk_(struct nvkm_object *, int, const char *, ...);
#define nv_printk(o,l,f,a...) do { \
if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG) \
nv_printk_(nv_object(o), NV_DBG_##l, f, ##a); \
} while(0)
#define nv_fatal(o,f,a...) nv_printk((o), FATAL, f, ##a)
#define nv_error(o,f,a...) nv_printk((o), ERROR, f, ##a)
#define nv_warn(o,f,a...) nv_printk((o), WARN, f, ##a)
#define nv_info(o,f,a...) nv_printk((o), INFO, f, ##a)
#define nv_debug(o,f,a...) nv_printk((o), DEBUG, f, ##a)
#define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a)
#define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a)
#define nv_ioctl(o,f,a...) nv_trace(nvkm_client(o), "ioctl: "f, ##a)
#define nv_assert(f,a...) do { \
if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG) \
nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a); \
BUG_ON(1); \
} while(0)
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
View file @ 3439633a
......@@ -2,19 +2,27 @@
#define __NVKM_RAMHT_H__
#include <core/gpuobj.h>
struct nvkm_ramht_data {
struct nvkm_gpuobj *inst;
int chid;
u32 handle;
};
struct nvkm_ramht {
struct nvkm_gpuobj gpuobj;
struct nvkm_device *device;
struct nvkm_gpuobj *parent;
struct nvkm_gpuobj *gpuobj;
int size;
int bits;
struct nvkm_ramht_data data[];
};
int nvkm_ramht_insert(struct nvkm_ramht *, int chid, u32 handle, u32 context);
int nvkm_ramht_new(struct nvkm_device *, u32 size, u32 align,
struct nvkm_gpuobj *, struct nvkm_ramht **);
void nvkm_ramht_del(struct nvkm_ramht **);
int nvkm_ramht_insert(struct nvkm_ramht *, struct nvkm_object *,
int chid, int addr, u32 handle, u32 context);
void nvkm_ramht_remove(struct nvkm_ramht *, int cookie);
int nvkm_ramht_new(struct nvkm_object *, struct nvkm_object *, u32 size,
u32 align, struct nvkm_ramht **);
static inline void
nvkm_ramht_ref(struct nvkm_ramht *obj, struct nvkm_ramht **ref)
{
nvkm_gpuobj_ref(&obj->gpuobj, (struct nvkm_gpuobj **)ref);
}
struct nvkm_gpuobj *
nvkm_ramht_search(struct nvkm_ramht *, int chid, u32 handle);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
View file @ 3439633a
#ifndef __NVKM_SUBDEV_H__
#define __NVKM_SUBDEV_H__
#include <core/object.h>
#include <core/devidx.h>
#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub))
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
#include <core/device.h>
struct nvkm_subdev {
struct nvkm_object object;
const struct nvkm_subdev_func *func;
struct nvkm_device *device;
enum nvkm_devidx index;
u32 pmc_enable;
struct mutex mutex;
const char *name;
void __iomem *mmio;
u32 debug;
u32 unit;
void (*intr)(struct nvkm_subdev *);
bool oneinit;
};
static inline struct nvkm_subdev *
nv_subdev(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_SUBDEV_CLASS)))
nv_assert("BAD CAST -> NvSubDev, %08x", nv_hclass(obj));
#endif
return obj;
}
static inline int
nv_subidx(struct nvkm_subdev *subdev)
{
return nv_hclass(subdev) & 0xff;
}
struct nvkm_subdev *nvkm_subdev(void *obj, int idx);
#define nvkm_subdev_create(p,e,o,v,s,f,d) \
nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \
sizeof(**d),(void **)d)
struct nvkm_subdev_func {
void *(*dtor)(struct nvkm_subdev *);
int (*preinit)(struct nvkm_subdev *);
int (*oneinit)(struct nvkm_subdev *);
int (*init)(struct nvkm_subdev *);
int (*fini)(struct nvkm_subdev *, bool suspend);
void (*intr)(struct nvkm_subdev *);
};
int nvkm_subdev_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32 pclass,
const char *sname, const char *fname,
int size, void **);
void nvkm_subdev_destroy(struct nvkm_subdev *);
extern const char *nvkm_subdev_name[NVKM_SUBDEV_NR];
void nvkm_subdev_ctor(const struct nvkm_subdev_func *, struct nvkm_device *,
int index, u32 pmc_enable, struct nvkm_subdev *);
void nvkm_subdev_del(struct nvkm_subdev **);
int nvkm_subdev_preinit(struct nvkm_subdev *);
int nvkm_subdev_init(struct nvkm_subdev *);
int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend);
void nvkm_subdev_reset(struct nvkm_object *);
void _nvkm_subdev_dtor(struct nvkm_object *);
int _nvkm_subdev_init(struct nvkm_object *);
int _nvkm_subdev_fini(struct nvkm_object *, bool suspend);
#define s_printk(s,l,f,a...) do { \
if ((s)->debug >= OS_DBG_##l) { \
nv_printk((s)->base.parent, (s)->name, l, f, ##a); \
void nvkm_subdev_intr(struct nvkm_subdev *);
/* subdev logging */
#define nvkm_printk_(s,l,p,f,a...) do { \
struct nvkm_subdev *_subdev = (s); \
if (_subdev->debug >= (l)) { \
dev_##p(_subdev->device->dev, "%s: "f, \
nvkm_subdev_name[_subdev->index], ##a); \
} \
} while(0)
static inline u8
nv_rd08(void *obj, u32 addr)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
u8 data = ioread8(subdev->mmio + addr);
nv_spam(subdev, "nv_rd08 0x%06x 0x%02x\n", addr, data);
return data;
}
static inline u16
nv_rd16(void *obj, u32 addr)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
u16 data = ioread16_native(subdev->mmio + addr);
nv_spam(subdev, "nv_rd16 0x%06x 0x%04x\n", addr, data);
return data;
}
static inline u32
nv_rd32(void *obj, u32 addr)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
u32 data = ioread32_native(subdev->mmio + addr);
nv_spam(subdev, "nv_rd32 0x%06x 0x%08x\n", addr, data);
return data;
}
static inline void
nv_wr08(void *obj, u32 addr, u8 data)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr08 0x%06x 0x%02x\n", addr, data);
iowrite8(data, subdev->mmio + addr);
}
static inline void
nv_wr16(void *obj, u32 addr, u16 data)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr16 0x%06x 0x%04x\n", addr, data);
iowrite16_native(data, subdev->mmio + addr);
}
static inline void
nv_wr32(void *obj, u32 addr, u32 data)
{
struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr32 0x%06x 0x%08x\n", addr, data);
iowrite32_native(data, subdev->mmio + addr);
}
static inline u32
nv_mask(void *obj, u32 addr, u32 mask, u32 data)
{
u32 temp = nv_rd32(obj, addr);
nv_wr32(obj, addr, (temp & ~mask) | data);
return temp;
}
#define nvkm_printk(s,l,p,f,a...) nvkm_printk_((s), NV_DBG_##l, p, f, ##a)
#define nvkm_fatal(s,f,a...) nvkm_printk((s), FATAL, crit, f, ##a)
#define nvkm_error(s,f,a...) nvkm_printk((s), ERROR, err, f, ##a)
#define nvkm_warn(s,f,a...) nvkm_printk((s), WARN, notice, f, ##a)
#define nvkm_info(s,f,a...) nvkm_printk((s), INFO, info, f, ##a)
#define nvkm_debug(s,f,a...) nvkm_printk((s), DEBUG, info, f, ##a)
#define nvkm_trace(s,f,a...) nvkm_printk((s), TRACE, info, f, ##a)
#define nvkm_spam(s,f,a...) nvkm_printk((s), SPAM, dbg, f, ##a)
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_DEVICE_TEGRA_H__
#define __NVKM_DEVICE_TEGRA_H__
#include <core/device.h>
#include <core/mm.h>
struct nvkm_device_tegra {
struct nvkm_device device;
struct platform_device *pdev;
int irq;
struct reset_control *rst;
struct clk *clk;
struct clk *clk_pwr;
struct regulator *vdd;
struct {
/*
* Protects accesses to mm from subsystems
*/
struct mutex mutex;
struct nvkm_mm mm;
struct iommu_domain *domain;
unsigned long pgshift;
} iommu;
int gpu_speedo;
};
int nvkm_device_tegra_new(struct platform_device *,
const char *cfg, const char *dbg,
bool detect, bool mmio, u64 subdev_mask,
struct nvkm_device **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
View file @ 3439633a
#ifndef __NVKM_BSP_H__
#define __NVKM_BSP_H__
#include <core/engine.h>
extern struct nvkm_oclass g84_bsp_oclass;
#include <engine/xtensa.h>
int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
View file @ 3439633a
#ifndef __NVKM_CE_H__
#define __NVKM_CE_H__
#include <core/engine.h>
#include <engine/falcon.h>
void gt215_ce_intr(struct nvkm_subdev *);
extern struct nvkm_oclass gt215_ce_oclass;
extern struct nvkm_oclass gf100_ce0_oclass;
extern struct nvkm_oclass gf100_ce1_oclass;
extern struct nvkm_oclass gk104_ce0_oclass;
extern struct nvkm_oclass gk104_ce1_oclass;
extern struct nvkm_oclass gk104_ce2_oclass;
extern struct nvkm_oclass gm204_ce0_oclass;
extern struct nvkm_oclass gm204_ce1_oclass;
extern struct nvkm_oclass gm204_ce2_oclass;
int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
int gm204_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
View file @ 3439633a
#ifndef __NVKM_CIPHER_H__
#define __NVKM_CIPHER_H__
#include <core/engine.h>
extern struct nvkm_oclass g84_cipher_oclass;
int g84_cipher_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/device.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NOUVEAU_SUBDEV_DEVICE_H__
#define __NOUVEAU_SUBDEV_DEVICE_H__
#include <core/device.h>
struct platform_device;
enum nv_bus_type {
NOUVEAU_BUS_PCI,
NOUVEAU_BUS_PLATFORM,
};
#define nouveau_device_create(p,t,n,s,c,d,u) \
nouveau_device_create_((void *)(p), (t), (n), (s), (c), (d), \
sizeof(**u), (void **)u)
int nouveau_device_create_(void *, enum nv_bus_type type, u64 name,
const char *sname, const char *cfg, const char *dbg,
int, void **);
int nv04_identify(struct nouveau_device *);
int nv10_identify(struct nouveau_device *);
int nv20_identify(struct nouveau_device *);
int nv30_identify(struct nouveau_device *);
int nv40_identify(struct nouveau_device *);
int nv50_identify(struct nouveau_device *);
int nvc0_identify(struct nouveau_device *);
int nve0_identify(struct nouveau_device *);
int gm100_identify(struct nouveau_device *);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
View file @ 3439633a
#ifndef __NVKM_DISP_H__
#define __NVKM_DISP_H__
#define nvkm_disp(p) container_of((p), struct nvkm_disp, engine)
#include <core/engine.h>
#include <core/event.h>
struct nvkm_disp {
struct nvkm_engine base;
const struct nvkm_disp_func *func;
struct nvkm_engine engine;
struct nvkm_oproxy *client;
struct list_head outp;
struct list_head conn;
struct nvkm_event hpd;
struct nvkm_event vblank;
};
static inline struct nvkm_disp *
nvkm_disp(void *obj)
{
return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP);
}
struct {
int nr;
} head;
};
extern struct nvkm_oclass *nv04_disp_oclass;
extern struct nvkm_oclass *nv50_disp_oclass;
extern struct nvkm_oclass *g84_disp_oclass;
extern struct nvkm_oclass *gt200_disp_oclass;
extern struct nvkm_oclass *g94_disp_oclass;
extern struct nvkm_oclass *gt215_disp_oclass;
extern struct nvkm_oclass *gf110_disp_oclass;
extern struct nvkm_oclass *gk104_disp_oclass;
extern struct nvkm_oclass *gk110_disp_oclass;
extern struct nvkm_oclass *gm107_disp_oclass;
extern struct nvkm_oclass *gm204_disp_oclass;
int nv04_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int nv50_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int g84_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gt200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int g94_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gt215_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gf119_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gk104_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gk110_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gm107_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gm204_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_DMA_H__
#define __NVKM_DMA_H__
#include <core/engine.h>
struct nvkm_client;
struct nvkm_dmaobj {
const struct nvkm_dmaobj_func *func;
struct nvkm_dma *dma;
struct nvkm_object object;
u32 target;
u32 access;
u64 start;
u64 limit;
struct rb_node rb;
u64 handle; /*XXX HANDLE MERGE */
};
struct nvkm_dma {
const struct nvkm_dma_func *func;
struct nvkm_engine engine;
};
struct nvkm_dmaobj *
nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object);
int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h deleted 100644 → 0
View file @ d7b27368
#ifndef __NVKM_DMAOBJ_H__
#define __NVKM_DMAOBJ_H__
#include <core/engine.h>
struct nvkm_gpuobj;
struct nvkm_dmaobj {
struct nvkm_object base;
u32 target;
u32 access;
u64 start;
u64 limit;
};
struct nvkm_dmaeng {
struct nvkm_engine base;
/* creates a "physical" dma object from a struct nvkm_dmaobj */
int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
struct nvkm_gpuobj **);
};
extern struct nvkm_oclass *nv04_dmaeng_oclass;
extern struct nvkm_oclass *nv50_dmaeng_oclass;
extern struct nvkm_oclass *gf100_dmaeng_oclass;
extern struct nvkm_oclass *gf110_dmaeng_oclass;
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
View file @ 3439633a
#ifndef __NVKM_FALCON_H__
#define __NVKM_FALCON_H__
#include <core/engctx.h>
struct nvkm_falcon_chan {
struct nvkm_engctx base;
};
#define nvkm_falcon_context_create(p,e,c,g,s,a,f,d) \
nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
#define nvkm_falcon_context_destroy(d) \
nvkm_engctx_destroy(&(d)->base)
#define nvkm_falcon_context_init(d) \
nvkm_engctx_init(&(d)->base)
#define nvkm_falcon_context_fini(d,s) \
nvkm_engctx_fini(&(d)->base, (s))
#define _nvkm_falcon_context_ctor _nvkm_engctx_ctor
#define _nvkm_falcon_context_dtor _nvkm_engctx_dtor
#define _nvkm_falcon_context_init _nvkm_engctx_init
#define _nvkm_falcon_context_fini _nvkm_engctx_fini
#define _nvkm_falcon_context_rd32 _nvkm_engctx_rd32
#define _nvkm_falcon_context_wr32 _nvkm_engctx_wr32
struct nvkm_falcon_data {
bool external;
};
#define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
#include <core/engine.h>
struct nvkm_fifo_chan;
struct nvkm_falcon {
struct nvkm_engine base;
const struct nvkm_falcon_func *func;
struct nvkm_engine engine;
u32 addr;
u8 version;
u8 secret;
struct nvkm_gpuobj *core;
struct nvkm_memory *core;
bool external;
struct {
......@@ -51,31 +28,21 @@ struct nvkm_falcon {
} data;
};
#define nv_falcon(priv) (&(priv)->base)
#define nvkm_falcon_create(p,e,c,b,d,i,f,r) \
nvkm_falcon_create_((p), (e), (c), (b), (d), (i), (f), \
sizeof(**r),(void **)r)
#define nvkm_falcon_destroy(p) \
nvkm_engine_destroy(&(p)->base)
#define nvkm_falcon_init(p) ({ \
struct nvkm_falcon *falcon = (p); \
_nvkm_falcon_init(nv_object(falcon)); \
})
#define nvkm_falcon_fini(p,s) ({ \
struct nvkm_falcon *falcon = (p); \
_nvkm_falcon_fini(nv_object(falcon), (s)); \
})
int nvkm_falcon_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, u32, bool, const char *,
const char *, int, void **);
int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
int index, bool enable, u32 addr, struct nvkm_engine **);
void nvkm_falcon_intr(struct nvkm_subdev *subdev);
#define _nvkm_falcon_dtor _nvkm_engine_dtor
int _nvkm_falcon_init(struct nvkm_object *);
int _nvkm_falcon_fini(struct nvkm_object *, bool);
u32 _nvkm_falcon_rd32(struct nvkm_object *, u64);
void _nvkm_falcon_wr32(struct nvkm_object *, u64, u32);
struct nvkm_falcon_func {
struct {
u32 *data;
u32 size;
} code;
struct {
u32 *data;
u32 size;
} data;
u32 pmc_enable;
void (*init)(struct nvkm_falcon *);
void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *);
struct nvkm_sclass sclass[];
};
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View file @ 3439633a
#ifndef __NVKM_FIFO_H__
#define __NVKM_FIFO_H__
#include <core/namedb.h>
#include <core/engine.h>
#include <core/event.h>
#define NVKM_FIFO_CHID_NR 4096
struct nvkm_fifo_engn {
struct nvkm_object *object;
int refcount;
int usecount;
};
struct nvkm_fifo_chan {
struct nvkm_namedb namedb;
struct nvkm_dmaobj *pushdma;
struct nvkm_gpuobj *pushgpu;
const struct nvkm_fifo_chan_func *func;
struct nvkm_fifo *fifo;
u64 engines;
struct nvkm_object object;
struct list_head head;
u16 chid;
struct nvkm_gpuobj *inst;
struct nvkm_gpuobj *push;
struct nvkm_vm *vm;
void __iomem *user;
u64 addr;
u32 size;
u16 chid;
atomic_t refcnt; /* NV04_NVSW_SET_REF */
};
static inline struct nvkm_fifo_chan *
nvkm_fifo_chan(void *obj)
{
return (void *)nv_namedb(obj);
}
#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \
nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
(m), sizeof(**d), (void **)d)
#define nvkm_fifo_channel_init(p) \
nvkm_namedb_init(&(p)->namedb)
#define nvkm_fifo_channel_fini(p,s) \
nvkm_namedb_fini(&(p)->namedb, (s))
int nvkm_fifo_channel_create_(struct nvkm_object *,
struct nvkm_object *,
struct nvkm_oclass *,
int bar, u32 addr, u32 size, u32 push,
u64 engmask, int len, void **);
void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *);
#define _nvkm_fifo_channel_init _nvkm_namedb_init
#define _nvkm_fifo_channel_fini _nvkm_namedb_fini
void _nvkm_fifo_channel_dtor(struct nvkm_object *);
int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *);
u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64);
void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32);
int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
#include <core/gpuobj.h>
struct nvkm_fifo_base {
struct nvkm_gpuobj gpuobj;
struct nvkm_fifo_engn engn[NVKM_SUBDEV_NR];
};
#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \
nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
#define nvkm_fifo_context_destroy(p) \
nvkm_gpuobj_destroy(&(p)->gpuobj)
#define nvkm_fifo_context_init(p) \
nvkm_gpuobj_init(&(p)->gpuobj)
#define nvkm_fifo_context_fini(p,s) \
nvkm_gpuobj_fini(&(p)->gpuobj, (s))
#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
#define _nvkm_fifo_context_init _nvkm_gpuobj_init
#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
#include <core/engine.h>
#include <core/event.h>
struct nvkm_fifo {
struct nvkm_engine base;
const struct nvkm_fifo_func *func;
struct nvkm_engine engine;
struct nvkm_event cevent; /* channel creation event */
struct nvkm_event uevent; /* async user trigger */
struct nvkm_object **channel;
DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR);
int nr;
struct list_head chan;
spinlock_t lock;
u16 min;
u16 max;
int (*chid)(struct nvkm_fifo *, struct nvkm_object *);
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
struct nvkm_event uevent; /* async user trigger */
struct nvkm_event cevent; /* channel creation event */
};
static inline struct nvkm_fifo *
nvkm_fifo(void *obj)
{
return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO);
}
#define nvkm_fifo_create(o,e,c,fc,lc,d) \
nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
#define nvkm_fifo_init(p) \
nvkm_engine_init(&(p)->base)
#define nvkm_fifo_fini(p,s) \
nvkm_engine_fini(&(p)->base, (s))
int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int min, int max,
int size, void **);
void nvkm_fifo_destroy(struct nvkm_fifo *);
const char *
nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid);
#define _nvkm_fifo_init _nvkm_engine_init
#define _nvkm_fifo_fini _nvkm_engine_fini
extern struct nvkm_oclass *nv04_fifo_oclass;
extern struct nvkm_oclass *nv10_fifo_oclass;
extern struct nvkm_oclass *nv17_fifo_oclass;
extern struct nvkm_oclass *nv40_fifo_oclass;
extern struct nvkm_oclass *nv50_fifo_oclass;
extern struct nvkm_oclass *g84_fifo_oclass;
extern struct nvkm_oclass *gf100_fifo_oclass;
extern struct nvkm_oclass *gk104_fifo_oclass;
extern struct nvkm_oclass *gk20a_fifo_oclass;
extern struct nvkm_oclass *gk208_fifo_oclass;
extern struct nvkm_oclass *gm204_fifo_oclass;
int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nvkm_fifo_uevent(struct nvkm_fifo *);
void nv04_fifo_intr(struct nvkm_subdev *);
int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *);
void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags,
struct nvkm_fifo_chan **);
struct nvkm_fifo_chan *
nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags);
struct nvkm_fifo_chan *
nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags);
int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View file @ 3439633a
#ifndef __NVKM_GR_H__
#define __NVKM_GR_H__
#include <core/engctx.h>
struct nvkm_gr_chan {
struct nvkm_engctx base;
};
#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \
nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
#define nvkm_gr_context_destroy(d) \
nvkm_engctx_destroy(&(d)->base)
#define nvkm_gr_context_init(d) \
nvkm_engctx_init(&(d)->base)
#define nvkm_gr_context_fini(d,s) \
nvkm_engctx_fini(&(d)->base, (s))
#define _nvkm_gr_context_dtor _nvkm_engctx_dtor
#define _nvkm_gr_context_init _nvkm_engctx_init
#define _nvkm_gr_context_fini _nvkm_engctx_fini
#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32
#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32
#include <core/engine.h>
struct nvkm_gr {
struct nvkm_engine base;
/* Returns chipset-specific counts of units packed into an u64.
*/
u64 (*units)(struct nvkm_gr *);
const struct nvkm_gr_func *func;
struct nvkm_engine engine;
};
static inline struct nvkm_gr *
nvkm_gr(void *obj)
{
return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR);
}
#define nvkm_gr_create(p,e,c,y,d) \
nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
#define nvkm_gr_destroy(d) \
nvkm_engine_destroy(&(d)->base)
#define nvkm_gr_init(d) \
nvkm_engine_init(&(d)->base)
#define nvkm_gr_fini(d,s) \
nvkm_engine_fini(&(d)->base, (s))
#define _nvkm_gr_dtor _nvkm_engine_dtor
#define _nvkm_gr_init _nvkm_engine_init
#define _nvkm_gr_fini _nvkm_engine_fini
extern struct nvkm_oclass nv04_gr_oclass;
extern struct nvkm_oclass nv10_gr_oclass;
extern struct nvkm_oclass nv20_gr_oclass;
extern struct nvkm_oclass nv25_gr_oclass;
extern struct nvkm_oclass nv2a_gr_oclass;
extern struct nvkm_oclass nv30_gr_oclass;
extern struct nvkm_oclass nv34_gr_oclass;
extern struct nvkm_oclass nv35_gr_oclass;
extern struct nvkm_oclass nv40_gr_oclass;
extern struct nvkm_oclass nv50_gr_oclass;
extern struct nvkm_oclass *gf100_gr_oclass;
extern struct nvkm_oclass *gf108_gr_oclass;
extern struct nvkm_oclass *gf104_gr_oclass;
extern struct nvkm_oclass *gf110_gr_oclass;
extern struct nvkm_oclass *gf117_gr_oclass;
extern struct nvkm_oclass *gf119_gr_oclass;
extern struct nvkm_oclass *gk104_gr_oclass;
extern struct nvkm_oclass *gk20a_gr_oclass;
extern struct nvkm_oclass *gk110_gr_oclass;
extern struct nvkm_oclass *gk110b_gr_oclass;
extern struct nvkm_oclass *gk208_gr_oclass;
extern struct nvkm_oclass *gm107_gr_oclass;
extern struct nvkm_oclass *gm204_gr_oclass;
extern struct nvkm_oclass *gm206_gr_oclass;
#include <core/enum.h>
extern const struct nvkm_bitfield nv04_gr_nsource[];
extern struct nvkm_ofuncs nv04_gr_ofuncs;
bool nv04_gr_idle(void *obj);
extern const struct nvkm_bitfield nv10_gr_intr_name[];
extern const struct nvkm_bitfield nv10_gr_nstatus[];
extern const struct nvkm_enum nv50_data_error_names[];
u64 nvkm_gr_units(struct nvkm_gr *);
int nvkm_gr_tlb_flush(struct nvkm_gr *);
int nv04_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv10_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv15_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv17_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv20_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv25_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv2a_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv30_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv34_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv35_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv40_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv44_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv50_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int g84_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gt200_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int mcp79_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gt215_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int mcp89_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf108_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf110_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf117_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf119_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk110_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk110b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk208_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk20a_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm204_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm206_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm20b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
View file @ 3439633a
#ifndef __NVKM_MPEG_H__
#define __NVKM_MPEG_H__
#include <core/engctx.h>
struct nvkm_mpeg_chan {
struct nvkm_engctx base;
};
#define nvkm_mpeg_context_create(p,e,c,g,s,a,f,d) \
nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
#define nvkm_mpeg_context_destroy(d) \
nvkm_engctx_destroy(&(d)->base)
#define nvkm_mpeg_context_init(d) \
nvkm_engctx_init(&(d)->base)
#define nvkm_mpeg_context_fini(d,s) \
nvkm_engctx_fini(&(d)->base, (s))
#define _nvkm_mpeg_context_dtor _nvkm_engctx_dtor
#define _nvkm_mpeg_context_init _nvkm_engctx_init
#define _nvkm_mpeg_context_fini _nvkm_engctx_fini
#define _nvkm_mpeg_context_rd32 _nvkm_engctx_rd32
#define _nvkm_mpeg_context_wr32 _nvkm_engctx_wr32
#include <core/engine.h>
struct nvkm_mpeg {
struct nvkm_engine base;
};
#define nvkm_mpeg_create(p,e,c,d) \
nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
#define nvkm_mpeg_destroy(d) \
nvkm_engine_destroy(&(d)->base)
#define nvkm_mpeg_init(d) \
nvkm_engine_init(&(d)->base)
#define nvkm_mpeg_fini(d,s) \
nvkm_engine_fini(&(d)->base, (s))
#define _nvkm_mpeg_dtor _nvkm_engine_dtor
#define _nvkm_mpeg_init _nvkm_engine_init
#define _nvkm_mpeg_fini _nvkm_engine_fini
extern struct nvkm_oclass nv31_mpeg_oclass;
extern struct nvkm_oclass nv40_mpeg_oclass;
extern struct nvkm_oclass nv44_mpeg_oclass;
extern struct nvkm_oclass nv50_mpeg_oclass;
extern struct nvkm_oclass g84_mpeg_oclass;
extern struct nvkm_ofuncs nv31_mpeg_ofuncs;
extern struct nvkm_oclass nv31_mpeg_cclass;
extern struct nvkm_oclass nv31_mpeg_sclass[];
extern struct nvkm_oclass nv40_mpeg_sclass[];
void nv31_mpeg_intr(struct nvkm_subdev *);
void nv31_mpeg_tile_prog(struct nvkm_engine *, int);
int nv31_mpeg_init(struct nvkm_object *);
extern struct nvkm_ofuncs nv50_mpeg_ofuncs;
int nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void nv50_mpeg_intr(struct nvkm_subdev *);
int nv50_mpeg_init(struct nvkm_object *);
int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
View file @ 3439633a
#ifndef __NVKM_MSPDEC_H__
#define __NVKM_MSPDEC_H__
#include <core/engine.h>
extern struct nvkm_oclass g98_mspdec_oclass;
extern struct nvkm_oclass gf100_mspdec_oclass;
extern struct nvkm_oclass gk104_mspdec_oclass;
#include <engine/falcon.h>
int g98_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gk104_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
View file @ 3439633a
#ifndef __NVKM_MSPPP_H__
#define __NVKM_MSPPP_H__
#include <core/engine.h>
extern struct nvkm_oclass g98_msppp_oclass;
extern struct nvkm_oclass gf100_msppp_oclass;
#include <engine/falcon.h>
int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
View file @ 3439633a
#ifndef __NVKM_MSVLD_H__
#define __NVKM_MSVLD_H__
#include <core/engine.h>
extern struct nvkm_oclass g98_msvld_oclass;
extern struct nvkm_oclass gf100_msvld_oclass;
extern struct nvkm_oclass gk104_msvld_oclass;
#include <engine/falcon.h>
int g98_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int mcp89_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gk104_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
View file @ 3439633a
......@@ -2,33 +2,24 @@
#define __NVKM_PM_H__
#include <core/engine.h>
struct nvkm_perfdom;
struct nvkm_perfctr;
struct nvkm_pm {
struct nvkm_engine base;
const struct nvkm_pm_func *func;
struct nvkm_engine engine;
struct nvkm_perfctx *context;
void *profile_data;
struct nvkm_object *perfmon;
struct list_head domains;
struct list_head sources;
u32 sequence;
/*XXX: temp for daemon backend */
u32 pwr[8];
u32 last;
};
static inline struct nvkm_pm *
nvkm_pm(void *obj)
{
return (void *)nvkm_engine(obj, NVDEV_ENGINE_PM);
}
extern struct nvkm_oclass *nv40_pm_oclass;
extern struct nvkm_oclass *nv50_pm_oclass;
extern struct nvkm_oclass *g84_pm_oclass;
extern struct nvkm_oclass *gt215_pm_oclass;
extern struct nvkm_oclass gf100_pm_oclass;
extern struct nvkm_oclass gk104_pm_oclass;
extern struct nvkm_oclass gk110_pm_oclass;
int nv40_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int nv50_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int g84_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gt200_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gt215_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf100_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf108_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf117_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gk104_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
View file @ 3439633a
#ifndef __NVKM_SEC_H__
#define __NVKM_SEC_H__
#include <core/engine.h>
extern struct nvkm_oclass g98_sec_oclass;
#include <engine/falcon.h>
int g98_sec_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
View file @ 3439633a
#ifndef __NVKM_SW_H__
#define __NVKM_SW_H__
#include <core/engctx.h>
struct nvkm_sw_chan {
struct nvkm_engctx base;
int (*flip)(void *);
void *flip_data;
};
#define nvkm_sw_context_create(p,e,c,d) \
nvkm_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
#define nvkm_sw_context_destroy(d) \
nvkm_engctx_destroy(&(d)->base)
#define nvkm_sw_context_init(d) \
nvkm_engctx_init(&(d)->base)
#define nvkm_sw_context_fini(d,s) \
nvkm_engctx_fini(&(d)->base, (s))
#define _nvkm_sw_context_dtor _nvkm_engctx_dtor
#define _nvkm_sw_context_init _nvkm_engctx_init
#define _nvkm_sw_context_fini _nvkm_engctx_fini
#include <core/engine.h>
struct nvkm_sw {
struct nvkm_engine base;
};
const struct nvkm_sw_func *func;
struct nvkm_engine engine;
#define nvkm_sw_create(p,e,c,d) \
nvkm_engine_create((p), (e), (c), true, "SW", "software", (d))
#define nvkm_sw_destroy(d) \
nvkm_engine_destroy(&(d)->base)
#define nvkm_sw_init(d) \
nvkm_engine_init(&(d)->base)
#define nvkm_sw_fini(d,s) \
nvkm_engine_fini(&(d)->base, (s))
#define _nvkm_sw_dtor _nvkm_engine_dtor
#define _nvkm_sw_init _nvkm_engine_init
#define _nvkm_sw_fini _nvkm_engine_fini
struct list_head chan;
};
extern struct nvkm_oclass *nv04_sw_oclass;
extern struct nvkm_oclass *nv10_sw_oclass;
extern struct nvkm_oclass *nv50_sw_oclass;
extern struct nvkm_oclass *gf100_sw_oclass;
bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data);
void nv04_sw_intr(struct nvkm_subdev *);
int nv04_sw_new(struct nvkm_device *, int, struct nvkm_sw **);
int nv10_sw_new(struct nvkm_device *, int, struct nvkm_sw **);
int nv50_sw_new(struct nvkm_device *, int, struct nvkm_sw **);
int gf100_sw_new(struct nvkm_device *, int, struct nvkm_sw **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
View file @ 3439633a
#ifndef __NVKM_VP_H__
#define __NVKM_VP_H__
#include <core/engine.h>
extern struct nvkm_oclass g84_vp_oclass;
#include <engine/xtensa.h>
int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
View file @ 3439633a
#ifndef __NVKM_XTENSA_H__
#define __NVKM_XTENSA_H__
#define nvkm_xtensa(p) container_of((p), struct nvkm_xtensa, engine)
#include <core/engine.h>
struct nvkm_gpuobj;
struct nvkm_xtensa {
struct nvkm_engine base;
const struct nvkm_xtensa_func *func;
u32 addr;
struct nvkm_gpuobj *gpu_fw;
u32 fifo_val;
u32 unkd28;
};
struct nvkm_engine engine;
#define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \
nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \
sizeof(**r),(void **)r)
struct nvkm_memory *gpu_fw;
};
int _nvkm_xtensa_engctx_ctor(struct nvkm_object *,
struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *,
int index, bool enable, u32 addr, struct nvkm_engine **);
void _nvkm_xtensa_intr(struct nvkm_subdev *);
int nvkm_xtensa_create_(struct nvkm_object *,
struct nvkm_object *,
struct nvkm_oclass *, u32, bool,
const char *, const char *,
int, void **);
#define _nvkm_xtensa_dtor _nvkm_engine_dtor
int _nvkm_xtensa_init(struct nvkm_object *);
int _nvkm_xtensa_fini(struct nvkm_object *, bool);
u32 _nvkm_xtensa_rd32(struct nvkm_object *, u64);
void _nvkm_xtensa_wr32(struct nvkm_object *, u64, u32);
struct nvkm_xtensa_func {
u32 pmc_enable;
u32 fifo_val;
u32 unkd28;
struct nvkm_sclass sclass[];
};
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
View file @ 3439633a
#ifndef __NVKM_BAR_H__
#define __NVKM_BAR_H__
#include <core/subdev.h>
struct nvkm_mem;
struct nvkm_vma;
struct nvkm_bar {
struct nvkm_subdev base;
const struct nvkm_bar_func *func;
struct nvkm_subdev subdev;
int (*alloc)(struct nvkm_bar *, struct nvkm_object *,
struct nvkm_mem *, struct nvkm_object **);
int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags,
struct nvkm_vma *);
int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags,
struct nvkm_vma *);
void (*unmap)(struct nvkm_bar *, struct nvkm_vma *);
void (*flush)(struct nvkm_bar *);
spinlock_t lock;
/* whether the BAR supports to be ioremapped WC or should be uncached */
bool iomap_uncached;
};
static inline struct nvkm_bar *
nvkm_bar(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR);
}
void nvkm_bar_flush(struct nvkm_bar *);
struct nvkm_vm *nvkm_bar_kmap(struct nvkm_bar *);
int nvkm_bar_umap(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
extern struct nvkm_oclass nv50_bar_oclass;
extern struct nvkm_oclass gf100_bar_oclass;
extern struct nvkm_oclass gk20a_bar_oclass;
int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
int gf100_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
int gk20a_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
View file @ 3439633a
......@@ -3,7 +3,7 @@
#include <core/subdev.h>
struct nvkm_bios {
struct nvkm_subdev base;
struct nvkm_subdev subdev;
u32 size;
u8 *data;
......@@ -19,14 +19,13 @@ struct nvkm_bios {
} version;
};
static inline struct nvkm_bios *
nvkm_bios(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VBIOS);
}
u8 nvbios_checksum(const u8 *data, int size);
u16 nvbios_findstr(const u8 *data, int size, const char *str, int len);
int nvbios_memcmp(struct nvkm_bios *, u32 addr, const char *, u32 len);
#define nvbios_rd08(b,o) (b)->data[(o)]
#define nvbios_rd16(b,o) get_unaligned_le16(&(b)->data[(o)])
#define nvbios_rd32(b,o) get_unaligned_le32(&(b)->data[(o)])
extern struct nvkm_oclass nvkm_bios_oclass;
int nvkm_bios_new(struct nvkm_device *, int, struct nvkm_bios **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
View file @ 3439633a
......@@ -4,8 +4,8 @@ static inline u16
bmp_version(struct nvkm_bios *bios)
{
if (bios->bmp_offset) {
return nv_ro08(bios, bios->bmp_offset + 5) << 8 |
nv_ro08(bios, bios->bmp_offset + 6);
return nvbios_rd08(bios, bios->bmp_offset + 5) << 8 |
nvbios_rd08(bios, bios->bmp_offset + 6);
}
return 0x0000;
......@@ -15,7 +15,7 @@ static inline u16
bmp_mem_init_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 24);
return nvbios_rd16(bios, bios->bmp_offset + 24);
return 0x0000;
}
......@@ -23,7 +23,7 @@ static inline u16
bmp_sdr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 26);
return nvbios_rd16(bios, bios->bmp_offset + 26);
return 0x0000;
}
......@@ -31,7 +31,7 @@ static inline u16
bmp_ddr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 28);
return nvbios_rd16(bios, bios->bmp_offset + 28);
return 0x0000;
}
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
View file @ 3439633a
#ifndef __NVBIOS_INIT_H__
#define __NVBIOS_INIT_H__
struct nvbios_init {
struct nvkm_subdev *subdev;
struct nvkm_bios *bios;
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
View file @ 3439633a
......@@ -6,6 +6,11 @@ struct nvbios_ramcfg {
unsigned rammap_min;
unsigned rammap_max;
union {
struct {
unsigned rammap_00_16_20:1;
unsigned rammap_00_16_40:1;
unsigned rammap_00_17_02:1;
};
struct {
unsigned rammap_10_04_02:1;
unsigned rammap_10_04_08:1;
......@@ -32,7 +37,25 @@ struct nvbios_ramcfg {
unsigned ramcfg_ver;
unsigned ramcfg_hdr;
unsigned ramcfg_timing;
unsigned ramcfg_DLLoff;
unsigned ramcfg_RON;
union {
struct {
unsigned ramcfg_00_03_01:1;
unsigned ramcfg_00_03_02:1;
unsigned ramcfg_00_03_08:1;
unsigned ramcfg_00_03_10:1;
unsigned ramcfg_00_04_02:1;
unsigned ramcfg_00_04_04:1;
unsigned ramcfg_00_04_20:1;
unsigned ramcfg_00_05:8;
unsigned ramcfg_00_06:8;
unsigned ramcfg_00_07:8;
unsigned ramcfg_00_08:8;
unsigned ramcfg_00_09:8;
unsigned ramcfg_00_0a_0f:4;
unsigned ramcfg_00_0a_f0:4;
};
struct {
unsigned ramcfg_10_02_01:1;
unsigned ramcfg_10_02_02:1;
......@@ -40,7 +63,6 @@ struct nvbios_ramcfg {
unsigned ramcfg_10_02_08:1;
unsigned ramcfg_10_02_10:1;
unsigned ramcfg_10_02_20:1;
unsigned ramcfg_10_DLLoff:1;
unsigned ramcfg_10_03_0f:4;
unsigned ramcfg_10_04_01:1;
unsigned ramcfg_10_05:8;
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
View file @ 3439633a
......@@ -7,6 +7,8 @@ u32 nvbios_rammapTe(struct nvkm_bios *, u8 *ver, u8 *hdr,
u32 nvbios_rammapEe(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_rammapEp_from_perf(struct nvkm_bios *bios, u32 data, u8 size,
struct nvbios_ramcfg *p);
u32 nvbios_rammapEp(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz,
......@@ -15,6 +17,8 @@ u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz,
u32 nvbios_rammapSe(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr);
u32 nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx,
struct nvbios_ramcfg *p);
u32 nvbios_rammapSp(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr, struct nvbios_ramcfg *);
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
View file @ 3439633a
......@@ -2,49 +2,23 @@
#define __NVKM_BUS_H__
#include <core/subdev.h>
struct nvkm_bus_intr {
u32 stat;
u32 unit;
};
struct nvkm_bus {
struct nvkm_subdev base;
int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
const struct nvkm_bus_func *func;
struct nvkm_subdev subdev;
};
static inline struct nvkm_bus *
nvkm_bus(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
}
#define nvkm_bus_create(p, e, o, d) \
nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
sizeof(**d), (void **)d)
#define nvkm_bus_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_bus_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_bus_fini(p, s) \
nvkm_subdev_fini(&(p)->base, (s))
#define _nvkm_bus_dtor _nvkm_subdev_dtor
#define _nvkm_bus_init _nvkm_subdev_init
#define _nvkm_bus_fini _nvkm_subdev_fini
extern struct nvkm_oclass *nv04_bus_oclass;
extern struct nvkm_oclass *nv31_bus_oclass;
extern struct nvkm_oclass *nv50_bus_oclass;
extern struct nvkm_oclass *g94_bus_oclass;
extern struct nvkm_oclass *gf100_bus_oclass;
/* interface to sequencer */
struct nvkm_hwsq;
int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **);
int nvkm_hwsq_init(struct nvkm_subdev *, struct nvkm_hwsq **);
int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);
int nv04_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int nv31_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int nv50_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int g94_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int gf100_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
View file @ 3439633a
......@@ -71,9 +71,10 @@ struct nvkm_domain {
};
struct nvkm_clk {
struct nvkm_subdev base;
const struct nvkm_clk_func *func;
struct nvkm_subdev subdev;
struct nvkm_domain *domains;
const struct nvkm_domain *domains;
struct nvkm_pstate bstate;
struct list_head states;
......@@ -94,68 +95,27 @@ struct nvkm_clk {
bool allow_reclock;
int (*read)(struct nvkm_clk *, enum nv_clk_src);
int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
int (*prog)(struct nvkm_clk *);
void (*tidy)(struct nvkm_clk *);
/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-nvkm_hw.c code
* bat-shit insane what-was-nouveau_hw.c code
*/
int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *pv);
int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
};
static inline struct nvkm_clk *
nvkm_clk(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK);
}
#define nvkm_clk_create(p,e,o,i,r,s,n,d) \
nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
(void **)d)
#define nvkm_clk_destroy(p) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_dtor(nv_object(clk)); \
})
#define nvkm_clk_init(p) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_init(nv_object(clk)); \
})
#define nvkm_clk_fini(p,s) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_fini(nv_object(clk), (s)); \
})
int nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *,
struct nvkm_domain *, struct nvkm_pstate *,
int, bool, int, void **);
void _nvkm_clk_dtor(struct nvkm_object *);
int _nvkm_clk_init(struct nvkm_object *);
int _nvkm_clk_fini(struct nvkm_object *, bool);
extern struct nvkm_oclass nv04_clk_oclass;
extern struct nvkm_oclass nv40_clk_oclass;
extern struct nvkm_oclass *nv50_clk_oclass;
extern struct nvkm_oclass *g84_clk_oclass;
extern struct nvkm_oclass *mcp77_clk_oclass;
extern struct nvkm_oclass gt215_clk_oclass;
extern struct nvkm_oclass gf100_clk_oclass;
extern struct nvkm_oclass gk104_clk_oclass;
extern struct nvkm_oclass gk20a_clk_oclass;
int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq);
int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *);
int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *,
int clk, struct nvkm_pll_vals *);
int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);
int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel);
int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
View file @ 3439633a
#ifndef __NVKM_DEVINIT_H__
#define __NVKM_DEVINIT_H__
#include <core/subdev.h>
struct nvkm_devinit;
struct nvkm_devinit {
struct nvkm_subdev base;
const struct nvkm_devinit_func *func;
struct nvkm_subdev subdev;
bool post;
void (*meminit)(struct nvkm_devinit *);
int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq);
u32 (*mmio)(struct nvkm_devinit *, u32 addr);
};
static inline struct nvkm_devinit *
nvkm_devinit(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_DEVINIT);
}
u32 nvkm_devinit_mmio(struct nvkm_devinit *, u32 addr);
int nvkm_devinit_pll_set(struct nvkm_devinit *, u32 type, u32 khz);
void nvkm_devinit_meminit(struct nvkm_devinit *);
u64 nvkm_devinit_disable(struct nvkm_devinit *);
int nvkm_devinit_post(struct nvkm_devinit *, u64 *disable);
extern struct nvkm_oclass *nv04_devinit_oclass;
extern struct nvkm_oclass *nv05_devinit_oclass;
extern struct nvkm_oclass *nv10_devinit_oclass;
extern struct nvkm_oclass *nv1a_devinit_oclass;
extern struct nvkm_oclass *nv20_devinit_oclass;
extern struct nvkm_oclass *nv50_devinit_oclass;
extern struct nvkm_oclass *g84_devinit_oclass;
extern struct nvkm_oclass *g98_devinit_oclass;
extern struct nvkm_oclass *gt215_devinit_oclass;
extern struct nvkm_oclass *mcp89_devinit_oclass;
extern struct nvkm_oclass *gf100_devinit_oclass;
extern struct nvkm_oclass *gm107_devinit_oclass;
extern struct nvkm_oclass *gm204_devinit_oclass;
int nv04_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv05_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv10_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv1a_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv20_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv50_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int g84_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int g98_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gt215_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int mcp89_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gf100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gm107_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gm204_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
View file @ 3439633a
......@@ -18,7 +18,7 @@
#define NV_MEM_TARGET_VM 3
#define NV_MEM_TARGET_GART 4
#define NV_MEM_TYPE_VM 0x7f
#define NVKM_RAM_TYPE_VM 0x7f
#define NV_MEM_COMP_VM 0x03
struct nvkm_mem {
......@@ -46,62 +46,47 @@ struct nvkm_fb_tile {
};
struct nvkm_fb {
struct nvkm_subdev base;
bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
const struct nvkm_fb_func *func;
struct nvkm_subdev subdev;
struct nvkm_ram *ram;
struct nvkm_mm vram;
struct nvkm_mm tags;
struct {
struct nvkm_fb_tile region[16];
int regions;
void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
} tile;
};
static inline struct nvkm_fb *
nvkm_fb(void *obj)
{
/* fbram uses this before device subdev pointer is valid */
if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
nv_subidx(obj) == NVDEV_SUBDEV_FB)
return obj;
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB);
}
extern struct nvkm_oclass *nv04_fb_oclass;
extern struct nvkm_oclass *nv10_fb_oclass;
extern struct nvkm_oclass *nv1a_fb_oclass;
extern struct nvkm_oclass *nv20_fb_oclass;
extern struct nvkm_oclass *nv25_fb_oclass;
extern struct nvkm_oclass *nv30_fb_oclass;
extern struct nvkm_oclass *nv35_fb_oclass;
extern struct nvkm_oclass *nv36_fb_oclass;
extern struct nvkm_oclass *nv40_fb_oclass;
extern struct nvkm_oclass *nv41_fb_oclass;
extern struct nvkm_oclass *nv44_fb_oclass;
extern struct nvkm_oclass *nv46_fb_oclass;
extern struct nvkm_oclass *nv47_fb_oclass;
extern struct nvkm_oclass *nv49_fb_oclass;
extern struct nvkm_oclass *nv4e_fb_oclass;
extern struct nvkm_oclass *nv50_fb_oclass;
extern struct nvkm_oclass *g84_fb_oclass;
extern struct nvkm_oclass *gt215_fb_oclass;
extern struct nvkm_oclass *mcp77_fb_oclass;
extern struct nvkm_oclass *mcp89_fb_oclass;
extern struct nvkm_oclass *gf100_fb_oclass;
extern struct nvkm_oclass *gk104_fb_oclass;
extern struct nvkm_oclass *gk20a_fb_oclass;
extern struct nvkm_oclass *gm107_fb_oclass;
bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
void nvkm_fb_tile_init(struct nvkm_fb *, int region, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nvkm_fb_tile_fini(struct nvkm_fb *, int region, struct nvkm_fb_tile *);
void nvkm_fb_tile_prog(struct nvkm_fb *, int region, struct nvkm_fb_tile *);
int nv04_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv10_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv1a_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv20_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv25_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv30_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv35_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv36_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv40_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv41_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv44_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv46_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv47_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv49_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv4e_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv50_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int g84_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gt215_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int mcp77_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int mcp89_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gf100_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gk104_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gk20a_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gm107_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
#include <subdev/bios.h>
#include <subdev/bios/ramcfg.h>
......@@ -112,36 +97,35 @@ struct nvkm_ram_data {
u32 freq;
};
enum nvkm_ram_type {
NVKM_RAM_TYPE_UNKNOWN = 0,
NVKM_RAM_TYPE_STOLEN,
NVKM_RAM_TYPE_SGRAM,
NVKM_RAM_TYPE_SDRAM,
NVKM_RAM_TYPE_DDR1,
NVKM_RAM_TYPE_DDR2,
NVKM_RAM_TYPE_DDR3,
NVKM_RAM_TYPE_GDDR2,
NVKM_RAM_TYPE_GDDR3,
NVKM_RAM_TYPE_GDDR4,
NVKM_RAM_TYPE_GDDR5
};
struct nvkm_ram {
struct nvkm_object base;
enum {
NV_MEM_TYPE_UNKNOWN = 0,
NV_MEM_TYPE_STOLEN,
NV_MEM_TYPE_SGRAM,
NV_MEM_TYPE_SDRAM,
NV_MEM_TYPE_DDR1,
NV_MEM_TYPE_DDR2,
NV_MEM_TYPE_DDR3,
NV_MEM_TYPE_GDDR2,
NV_MEM_TYPE_GDDR3,
NV_MEM_TYPE_GDDR4,
NV_MEM_TYPE_GDDR5
} type;
u64 stolen;
const struct nvkm_ram_func *func;
struct nvkm_fb *fb;
enum nvkm_ram_type type;
u64 size;
u32 tags;
#define NVKM_RAM_MM_SHIFT 12
struct nvkm_mm vram;
struct nvkm_mm tags;
u64 stolen;
int ranks;
int parts;
int part_mask;
int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc,
u32 type, struct nvkm_mem **);
void (*put)(struct nvkm_fb *, struct nvkm_mem **);
int (*calc)(struct nvkm_fb *, u32 freq);
int (*prog)(struct nvkm_fb *);
void (*tidy)(struct nvkm_fb *);
u32 freq;
u32 mr[16];
u32 mr1_nuts;
......@@ -151,4 +135,17 @@ struct nvkm_ram {
struct nvkm_ram_data xition;
struct nvkm_ram_data target;
};
struct nvkm_ram_func {
void *(*dtor)(struct nvkm_ram *);
int (*init)(struct nvkm_ram *);
int (*get)(struct nvkm_ram *, u64 size, u32 align, u32 size_nc,
u32 type, struct nvkm_mem **);
void (*put)(struct nvkm_ram *, struct nvkm_mem **);
int (*calc)(struct nvkm_ram *, u32 freq);
int (*prog)(struct nvkm_ram *);
void (*tidy)(struct nvkm_ram *);
};
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
View file @ 3439633a
#ifndef __NVKM_FUSE_H__
#define __NVKM_FUSE_H__
#include <core/subdev.h>
#include <core/device.h>
struct nvkm_fuse {
struct nvkm_subdev base;
const struct nvkm_fuse_func *func;
struct nvkm_subdev subdev;
spinlock_t lock;
};
static inline struct nvkm_fuse *
nvkm_fuse(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FUSE);
}
u32 nvkm_fuse_read(struct nvkm_fuse *, u32 addr);
#define nvkm_fuse_create(p, e, o, d) \
nvkm_fuse_create_((p), (e), (o), sizeof(**d), (void **)d)
int nvkm_fuse_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_fuse_dtor(struct nvkm_object *);
int _nvkm_fuse_init(struct nvkm_object *);
#define _nvkm_fuse_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv50_fuse_oclass;
extern struct nvkm_oclass gf100_fuse_oclass;
extern struct nvkm_oclass gm107_fuse_oclass;
int nv50_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **);
int gf100_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **);
int gm107_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
View file @ 3439633a
......@@ -19,26 +19,21 @@ struct nvkm_gpio_ntfy_rep {
};
struct nvkm_gpio {
struct nvkm_subdev base;
const struct nvkm_gpio_func *func;
struct nvkm_subdev subdev;
struct nvkm_event event;
void (*reset)(struct nvkm_gpio *, u8 func);
int (*find)(struct nvkm_gpio *, int idx, u8 tag, u8 line,
struct dcb_gpio_func *);
int (*set)(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state);
int (*get)(struct nvkm_gpio *, int idx, u8 tag, u8 line);
};
static inline struct nvkm_gpio *
nvkm_gpio(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_GPIO);
}
extern struct nvkm_oclass *nv10_gpio_oclass;
extern struct nvkm_oclass *nv50_gpio_oclass;
extern struct nvkm_oclass *g94_gpio_oclass;
extern struct nvkm_oclass *gf110_gpio_oclass;
extern struct nvkm_oclass *gk104_gpio_oclass;
void nvkm_gpio_reset(struct nvkm_gpio *, u8 func);
int nvkm_gpio_find(struct nvkm_gpio *, int idx, u8 tag, u8 line,
struct dcb_gpio_func *);
int nvkm_gpio_set(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state);
int nvkm_gpio_get(struct nvkm_gpio *, int idx, u8 tag, u8 line);
int nv10_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
int nv50_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
int g94_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
int gf119_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
int gk104_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
View file @ 3439633a
......@@ -6,15 +6,6 @@
#include <subdev/bios.h>
#include <subdev/bios/i2c.h>
#define NV_I2C_PORT(n) (0x00 + (n))
#define NV_I2C_AUX(n) (0x10 + (n))
#define NV_I2C_EXT(n) (0x20 + (n))
#define NV_I2C_DEFAULT(n) (0x80 + (n))
#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n))
#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8)
#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8)
struct nvkm_i2c_ntfy_req {
#define NVKM_I2C_PLUG 0x01
#define NVKM_I2C_UNPLUG 0x02
......@@ -29,72 +20,79 @@ struct nvkm_i2c_ntfy_rep {
u8 mask;
};
struct nvkm_i2c_port {
struct nvkm_object base;
struct i2c_adapter adapter;
struct mutex mutex;
struct nvkm_i2c_bus_probe {
struct i2c_board_info dev;
u8 udelay; /* set to 0 to use the standard delay */
};
struct list_head head;
u8 index;
int aux;
struct nvkm_i2c_bus {
const struct nvkm_i2c_bus_func *func;
struct nvkm_i2c_pad *pad;
#define NVKM_I2C_BUS_CCB(n) /* 'n' is ccb index */ (n)
#define NVKM_I2C_BUS_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100)
#define NVKM_I2C_BUS_PRI /* ccb primary comm. port */ -1
#define NVKM_I2C_BUS_SEC /* ccb secondary comm. port */ -2
int id;
const struct nvkm_i2c_func *func;
struct mutex mutex;
struct list_head head;
struct i2c_adapter i2c;
};
struct nvkm_i2c_func {
void (*drive_scl)(struct nvkm_i2c_port *, int);
void (*drive_sda)(struct nvkm_i2c_port *, int);
int (*sense_scl)(struct nvkm_i2c_port *);
int (*sense_sda)(struct nvkm_i2c_port *);
int nvkm_i2c_bus_acquire(struct nvkm_i2c_bus *);
void nvkm_i2c_bus_release(struct nvkm_i2c_bus *);
int nvkm_i2c_bus_probe(struct nvkm_i2c_bus *, const char *,
struct nvkm_i2c_bus_probe *,
bool (*)(struct nvkm_i2c_bus *,
struct i2c_board_info *, void *), void *);
int (*aux)(struct nvkm_i2c_port *, bool, u8, u32, u8 *, u8);
int (*pattern)(struct nvkm_i2c_port *, int pattern);
int (*lnk_ctl)(struct nvkm_i2c_port *, int nr, int bw, bool enh);
int (*drv_ctl)(struct nvkm_i2c_port *, int lane, int sw, int pe);
};
struct nvkm_i2c_aux {
const struct nvkm_i2c_aux_func *func;
struct nvkm_i2c_pad *pad;
#define NVKM_I2C_AUX_CCB(n) /* 'n' is ccb index */ (n)
#define NVKM_I2C_AUX_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100)
int id;
struct nvkm_i2c_board_info {
struct i2c_board_info dev;
u8 udelay; /* set to 0 to use the standard delay */
struct mutex mutex;
struct list_head head;
struct i2c_adapter i2c;
u32 intr;
};
void nvkm_i2c_aux_monitor(struct nvkm_i2c_aux *, bool monitor);
int nvkm_i2c_aux_acquire(struct nvkm_i2c_aux *);
void nvkm_i2c_aux_release(struct nvkm_i2c_aux *);
int nvkm_i2c_aux_xfer(struct nvkm_i2c_aux *, bool retry, u8 type,
u32 addr, u8 *data, u8 size);
int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
bool enhanced_framing);
struct nvkm_i2c {
struct nvkm_subdev base;
struct nvkm_event event;
const struct nvkm_i2c_func *func;
struct nvkm_subdev subdev;
struct nvkm_i2c_port *(*find)(struct nvkm_i2c *, u8 index);
struct nvkm_i2c_port *(*find_type)(struct nvkm_i2c *, u16 type);
int (*acquire_pad)(struct nvkm_i2c_port *, unsigned long timeout);
void (*release_pad)(struct nvkm_i2c_port *);
int (*acquire)(struct nvkm_i2c_port *, unsigned long timeout);
void (*release)(struct nvkm_i2c_port *);
int (*identify)(struct nvkm_i2c *, int index,
const char *what, struct nvkm_i2c_board_info *,
bool (*match)(struct nvkm_i2c_port *,
struct i2c_board_info *, void *),
void *);
wait_queue_head_t wait;
struct list_head ports;
struct list_head pad;
struct list_head bus;
struct list_head aux;
struct nvkm_event event;
};
static inline struct nvkm_i2c *
nvkm_i2c(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_I2C);
}
struct nvkm_i2c_bus *nvkm_i2c_bus_find(struct nvkm_i2c *, int);
struct nvkm_i2c_aux *nvkm_i2c_aux_find(struct nvkm_i2c *, int);
extern struct nvkm_oclass *nv04_i2c_oclass;
extern struct nvkm_oclass *nv4e_i2c_oclass;
extern struct nvkm_oclass *nv50_i2c_oclass;
extern struct nvkm_oclass *g94_i2c_oclass;
extern struct nvkm_oclass *gf110_i2c_oclass;
extern struct nvkm_oclass *gf117_i2c_oclass;
extern struct nvkm_oclass *gk104_i2c_oclass;
extern struct nvkm_oclass *gm204_i2c_oclass;
int nv04_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int nv4e_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int nv50_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int g94_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gf117_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gf119_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gk104_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gm204_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
static inline int
nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg)
nvkm_rdi2cr(struct i2c_adapter *adap, u8 addr, u8 reg)
{
u8 val;
struct i2c_msg msgs[] = {
......@@ -102,7 +100,7 @@ nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg)
{ .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val },
};
int ret = i2c_transfer(&port->adapter, msgs, 2);
int ret = i2c_transfer(adap, msgs, ARRAY_SIZE(msgs));
if (ret != 2)
return -EIO;
......@@ -110,14 +108,14 @@ nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg)
}
static inline int
nv_wri2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg, u8 val)
nvkm_wri2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msgs[] = {
{ .addr = addr, .flags = 0, .len = 2, .buf = buf },
};
int ret = i2c_transfer(&port->adapter, msgs, 1);
int ret = i2c_transfer(adap, msgs, ARRAY_SIZE(msgs));
if (ret != 1)
return -EIO;
......@@ -125,11 +123,30 @@ nv_wri2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg, u8 val)
}
static inline bool
nv_probe_i2c(struct nvkm_i2c_port *port, u8 addr)
nvkm_probe_i2c(struct i2c_adapter *adap, u8 addr)
{
return nv_rdi2cr(port, addr, 0) >= 0;
return nvkm_rdi2cr(adap, addr, 0) >= 0;
}
int nv_rdaux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size);
int nv_wraux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size);
static inline int
nvkm_rdaux(struct nvkm_i2c_aux *aux, u32 addr, u8 *data, u8 size)
{
int ret = nvkm_i2c_aux_acquire(aux);
if (ret == 0) {
ret = nvkm_i2c_aux_xfer(aux, true, 9, addr, data, size);
nvkm_i2c_aux_release(aux);
}
return ret;
}
static inline int
nvkm_wraux(struct nvkm_i2c_aux *aux, u32 addr, u8 *data, u8 size)
{
int ret = nvkm_i2c_aux_acquire(aux);
if (ret == 0) {
ret = nvkm_i2c_aux_xfer(aux, true, 8, addr, data, size);
nvkm_i2c_aux_release(aux);
}
return ret;
}
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
View file @ 3439633a
......@@ -2,31 +2,7 @@
#define __NVKM_IBUS_H__
#include <core/subdev.h>
struct nvkm_ibus {
struct nvkm_subdev base;
};
static inline struct nvkm_ibus *
nvkm_ibus(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_IBUS);
}
#define nvkm_ibus_create(p,e,o,d) \
nvkm_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \
sizeof(**d), (void **)d)
#define nvkm_ibus_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_ibus_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_ibus_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
#define _nvkm_ibus_dtor _nvkm_subdev_dtor
#define _nvkm_ibus_init _nvkm_subdev_init
#define _nvkm_ibus_fini _nvkm_subdev_fini
extern struct nvkm_oclass gf100_ibus_oclass;
extern struct nvkm_oclass gk104_ibus_oclass;
extern struct nvkm_oclass gk20a_ibus_oclass;
int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
View file @ 3439633a
#ifndef __NVKM_INSTMEM_H__
#define __NVKM_INSTMEM_H__
#include <core/subdev.h>
struct nvkm_instobj {
struct nvkm_object base;
struct list_head head;
u32 *suspend;
u64 addr;
u32 size;
};
static inline struct nvkm_instobj *
nv_memobj(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS)))
nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj));
#endif
return obj;
}
struct nvkm_memory;
struct nvkm_instmem {
struct nvkm_subdev base;
struct list_head list;
const struct nvkm_instmem_func *func;
struct nvkm_subdev subdev;
struct list_head list;
u32 reserved;
int (*alloc)(struct nvkm_instmem *, struct nvkm_object *,
u32 size, u32 align, struct nvkm_object **);
struct nvkm_memory *vbios;
struct nvkm_ramht *ramht;
struct nvkm_memory *ramro;
struct nvkm_memory *ramfc;
};
static inline struct nvkm_instmem *
nvkm_instmem(void *obj)
{
/* nv04/nv40 impls need to create objects in their constructor,
* which is before the subdev pointer is valid
*/
if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)
return obj;
u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr);
void nvkm_instmem_wr32(struct nvkm_instmem *, u32 addr, u32 data);
int nvkm_instobj_new(struct nvkm_instmem *, u32 size, u32 align, bool zero,
struct nvkm_memory **);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM);
}
extern struct nvkm_oclass *nv04_instmem_oclass;
extern struct nvkm_oclass *nv40_instmem_oclass;
extern struct nvkm_oclass *nv50_instmem_oclass;
extern struct nvkm_oclass *gk20a_instmem_oclass;
int nv04_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int nv40_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int nv50_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int gk20a_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
View file @ 3439633a
#ifndef __NVKM_LTC_H__
#define __NVKM_LTC_H__
#include <core/subdev.h>
struct nvkm_mm_node;
#include <core/mm.h>
#define NVKM_LTC_MAX_ZBC_CNT 16
struct nvkm_ltc {
struct nvkm_subdev base;
const struct nvkm_ltc_func *func;
struct nvkm_subdev subdev;
int (*tags_alloc)(struct nvkm_ltc *, u32 count,
struct nvkm_mm_node **);
void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **);
void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count);
u32 ltc_nr;
u32 lts_nr;
u32 num_tags;
u32 tag_base;
struct nvkm_mm tags;
struct nvkm_mm_node *tag_ram;
int zbc_min;
int zbc_max;
int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]);
int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32);
u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
};
static inline struct nvkm_ltc *
nvkm_ltc(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC);
}
int nvkm_ltc_tags_alloc(struct nvkm_ltc *, u32 count, struct nvkm_mm_node **);
void nvkm_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count);
int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]);
int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32);
extern struct nvkm_oclass *gf100_ltc_oclass;
extern struct nvkm_oclass *gk104_ltc_oclass;
extern struct nvkm_oclass *gm107_ltc_oclass;
int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
View file @ 3439633a
......@@ -3,26 +3,19 @@
#include <core/subdev.h>
struct nvkm_mc {
struct nvkm_subdev base;
bool use_msi;
unsigned int irq;
void (*unk260)(struct nvkm_mc *, u32);
const struct nvkm_mc_func *func;
struct nvkm_subdev subdev;
};
static inline struct nvkm_mc *
nvkm_mc(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC);
}
void nvkm_mc_intr(struct nvkm_mc *, bool *handled);
void nvkm_mc_intr_unarm(struct nvkm_mc *);
void nvkm_mc_intr_rearm(struct nvkm_mc *);
void nvkm_mc_unk260(struct nvkm_mc *, u32 data);
extern struct nvkm_oclass *nv04_mc_oclass;
extern struct nvkm_oclass *nv40_mc_oclass;
extern struct nvkm_oclass *nv44_mc_oclass;
extern struct nvkm_oclass *nv4c_mc_oclass;
extern struct nvkm_oclass *nv50_mc_oclass;
extern struct nvkm_oclass *g94_mc_oclass;
extern struct nvkm_oclass *g98_mc_oclass;
extern struct nvkm_oclass *gf100_mc_oclass;
extern struct nvkm_oclass *gf106_mc_oclass;
extern struct nvkm_oclass *gk20a_mc_oclass;
int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int g98_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int gf100_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View file @ 3439633a
......@@ -6,7 +6,7 @@ struct nvkm_device;
struct nvkm_mem;
struct nvkm_vm_pgt {
struct nvkm_gpuobj *obj[2];
struct nvkm_memory *mem[2];
u32 refcount[2];
};
......@@ -26,74 +26,23 @@ struct nvkm_vma {
struct nvkm_vm {
struct nvkm_mmu *mmu;
struct mutex mutex;
struct nvkm_mm mm;
struct kref refcount;
struct list_head pgd_list;
atomic_t engref[NVDEV_SUBDEV_NR];
atomic_t engref[NVKM_SUBDEV_NR];
struct nvkm_vm_pgt *pgt;
u32 fpde;
u32 lpde;
};
struct nvkm_mmu {
struct nvkm_subdev base;
u64 limit;
u8 dma_bits;
u32 pgt_bits;
u8 spg_shift;
u8 lpg_shift;
int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
u64 mm_offset, struct nvkm_vm **);
void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
struct nvkm_gpuobj *pgt[2]);
void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta);
void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
void (*flush)(struct nvkm_vm *);
};
static inline struct nvkm_mmu *
nvkm_mmu(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
}
#define nvkm_mmu_create(p,e,o,i,f,d) \
nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
#define nvkm_mmu_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_mmu_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_mmu_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
#define _nvkm_mmu_dtor _nvkm_subdev_dtor
#define _nvkm_mmu_init _nvkm_subdev_init
#define _nvkm_mmu_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv04_mmu_oclass;
extern struct nvkm_oclass nv41_mmu_oclass;
extern struct nvkm_oclass nv44_mmu_oclass;
extern struct nvkm_oclass nv50_mmu_oclass;
extern struct nvkm_oclass gf100_mmu_oclass;
int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
struct nvkm_vm **);
void nv04_mmu_dtor(struct nvkm_object *);
int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
u32 block, struct nvkm_vm **);
int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
struct nvkm_vm **);
struct lock_class_key *, struct nvkm_vm **);
int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
int nvkm_vm_boot(struct nvkm_vm *, u64 size);
int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
struct nvkm_vma *);
void nvkm_vm_put(struct nvkm_vma *);
......@@ -101,4 +50,19 @@ void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
void nvkm_vm_unmap(struct nvkm_vma *);
void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
struct nvkm_mmu {
const struct nvkm_mmu_func *func;
struct nvkm_subdev subdev;
u64 limit;
u8 dma_bits;
u8 lpg_shift;
};
int nv04_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
View file @ 3439633a
......@@ -2,33 +2,5 @@
#define __NVKM_MXM_H__
#include <core/subdev.h>
#define MXM_SANITISE_DCB 0x00000001
struct nvkm_mxm {
struct nvkm_subdev base;
u32 action;
u8 *mxms;
};
static inline struct nvkm_mxm *
nvkm_mxm(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MXM);
}
#define nvkm_mxm_create(p,e,o,d) \
nvkm_mxm_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_mxm_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_mxm_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
int nvkm_mxm_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void nvkm_mxm_destroy(struct nvkm_mxm *);
#define _nvkm_mxm_dtor _nvkm_subdev_dtor
#define _nvkm_mxm_init _nvkm_subdev_init
#define _nvkm_mxm_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv50_mxm_oclass;
int nv50_mxm_new(struct nvkm_device *, int, struct nvkm_subdev **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h 0 → 100644
View file @ 3439633a
#ifndef __NVKM_PCI_H__
#define __NVKM_PCI_H__
#include <core/subdev.h>
struct nvkm_pci {
const struct nvkm_pci_func *func;
struct nvkm_subdev subdev;
struct pci_dev *pdev;
int irq;
struct {
struct agp_bridge_data *bridge;
u32 mode;
u64 base;
u64 size;
int mtrr;
bool cma;
bool acquired;
} agp;
bool msi;
};
u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr);
void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data);
void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int nv50_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
View file @ 3439633a
......@@ -3,7 +3,8 @@
#include <core/subdev.h>
struct nvkm_pmu {
struct nvkm_subdev base;
const struct nvkm_pmu_func *func;
struct nvkm_subdev subdev;
struct {
u32 base;
......@@ -20,24 +21,20 @@ struct nvkm_pmu {
u32 message;
u32 data[2];
} recv;
int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
void (*pgob)(struct nvkm_pmu *, bool);
};
static inline struct nvkm_pmu *
nvkm_pmu(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU);
}
extern struct nvkm_oclass *gt215_pmu_oclass;
extern struct nvkm_oclass *gf100_pmu_oclass;
extern struct nvkm_oclass *gf110_pmu_oclass;
extern struct nvkm_oclass *gk104_pmu_oclass;
extern struct nvkm_oclass *gk110_pmu_oclass;
extern struct nvkm_oclass *gk208_pmu_oclass;
extern struct nvkm_oclass *gk20a_pmu_oclass;
int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process,
u32 message, u32 data0, u32 data1);
void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable);
int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
/* interface to MEMX process running on PMU */
struct nvkm_memx;
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
View file @ 3439633a
......@@ -2,6 +2,28 @@
#define __NVKM_THERM_H__
#include <core/subdev.h>
#include <subdev/bios.h>
#include <subdev/bios/therm.h>
#include <subdev/timer.h>
enum nvkm_therm_thrs_direction {
NVKM_THERM_THRS_FALLING = 0,
NVKM_THERM_THRS_RISING = 1
};
enum nvkm_therm_thrs_state {
NVKM_THERM_THRS_LOWER = 0,
NVKM_THERM_THRS_HIGHER = 1
};
enum nvkm_therm_thrs {
NVKM_THERM_THRS_FANBOOST = 0,
NVKM_THERM_THRS_DOWNCLOCK = 1,
NVKM_THERM_THRS_CRITICAL = 2,
NVKM_THERM_THRS_SHUTDOWN = 3,
NVKM_THERM_THRS_NR
};
enum nvkm_therm_fan_mode {
NVKM_THERM_CTRL_NONE = 0,
NVKM_THERM_CTRL_MANUAL = 1,
......@@ -24,56 +46,54 @@ enum nvkm_therm_attr_type {
};
struct nvkm_therm {
struct nvkm_subdev base;
const struct nvkm_therm_func *func;
struct nvkm_subdev subdev;
int (*pwm_ctrl)(struct nvkm_therm *, int line, bool);
int (*pwm_get)(struct nvkm_therm *, int line, u32 *, u32 *);
int (*pwm_set)(struct nvkm_therm *, int line, u32, u32);
int (*pwm_clock)(struct nvkm_therm *, int line);
/* automatic thermal management */
struct nvkm_alarm alarm;
spinlock_t lock;
struct nvbios_therm_trip_point *last_trip;
int mode;
int cstate;
int suspend;
/* bios */
struct nvbios_therm_sensor bios_sensor;
/* fan priv */
struct nvkm_fan *fan;
/* alarms priv */
struct {
spinlock_t alarm_program_lock;
struct nvkm_alarm therm_poll_alarm;
enum nvkm_therm_thrs_state alarm_state[NVKM_THERM_THRS_NR];
} sensor;
/* what should be done if the card overheats */
struct {
void (*downclock)(struct nvkm_therm *, bool active);
void (*pause)(struct nvkm_therm *, bool active);
} emergency;
/* ic */
struct i2c_client *ic;
int (*fan_get)(struct nvkm_therm *);
int (*fan_set)(struct nvkm_therm *, int);
int (*fan_sense)(struct nvkm_therm *);
int (*temp_get)(struct nvkm_therm *);
int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type);
int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int);
};
static inline struct nvkm_therm *
nvkm_therm(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_THERM);
}
#define nvkm_therm_create(p,e,o,d) \
nvkm_therm_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_therm_destroy(p) ({ \
struct nvkm_therm *therm = (p); \
_nvkm_therm_dtor(nv_object(therm)); \
})
#define nvkm_therm_init(p) ({ \
struct nvkm_therm *therm = (p); \
_nvkm_therm_init(nv_object(therm)); \
})
#define nvkm_therm_fini(p,s) ({ \
struct nvkm_therm *therm = (p); \
_nvkm_therm_init(nv_object(therm), (s)); \
})
int nvkm_therm_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_therm_dtor(struct nvkm_object *);
int _nvkm_therm_init(struct nvkm_object *);
int _nvkm_therm_fini(struct nvkm_object *, bool);
int nvkm_therm_temp_get(struct nvkm_therm *);
int nvkm_therm_fan_sense(struct nvkm_therm *);
int nvkm_therm_cstate(struct nvkm_therm *, int, int);
extern struct nvkm_oclass nv40_therm_oclass;
extern struct nvkm_oclass nv50_therm_oclass;
extern struct nvkm_oclass g84_therm_oclass;
extern struct nvkm_oclass gt215_therm_oclass;
extern struct nvkm_oclass gf110_therm_oclass;
extern struct nvkm_oclass gm107_therm_oclass;
int nv40_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
int nv50_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
View file @ 3439633a
......@@ -9,53 +9,58 @@ struct nvkm_alarm {
};
static inline void
nvkm_alarm_init(struct nvkm_alarm *alarm,
void (*func)(struct nvkm_alarm *))
nvkm_alarm_init(struct nvkm_alarm *alarm, void (*func)(struct nvkm_alarm *))
{
INIT_LIST_HEAD(&alarm->head);
alarm->func = func;
}
bool nvkm_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data);
bool nvkm_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data);
bool nvkm_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data);
void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *);
void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *);
#define NV_WAIT_DEFAULT 2000000000ULL
#define nv_wait(o,a,m,v) \
nvkm_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v))
#define nv_wait_ne(o,a,m,v) \
nvkm_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v))
#define nv_wait_cb(o,c,d) \
nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
struct nvkm_timer {
struct nvkm_subdev base;
u64 (*read)(struct nvkm_timer *);
void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *);
void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *);
};
const struct nvkm_timer_func *func;
struct nvkm_subdev subdev;
static inline struct nvkm_timer *
nvkm_timer(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER);
}
struct list_head alarms;
spinlock_t lock;
};
#define nvkm_timer_create(p,e,o,d) \
nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \
sizeof(**d), (void **)d)
#define nvkm_timer_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_timer_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_timer_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
u64 nvkm_timer_read(struct nvkm_timer *);
void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *);
void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *);
int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *,
struct nvkm_oclass *, int size, void **);
/* Delay based on GPU time (ie. PTIMER).
*
* Will return -ETIMEDOUT unless the loop was terminated with 'break',
* where it will return the number of nanoseconds taken instead.
*
* NVKM_DELAY can be passed for 'cond' to disable the timeout warning,
* which is useful for unconditional delay loops.
*/
#define NVKM_DELAY _warn = false;
#define nvkm_nsec(d,n,cond...) ({ \
struct nvkm_device *_device = (d); \
struct nvkm_timer *_tmr = _device->timer; \
u64 _nsecs = (n), _time0 = nvkm_timer_read(_tmr); \
s64 _taken = 0; \
bool _warn = true; \
\
do { \
cond \
} while (_taken = nvkm_timer_read(_tmr) - _time0, _taken < _nsecs); \
\
if (_taken >= _nsecs) { \
if (_warn) { \
dev_warn(_device->dev, "timeout at %s:%d/%s()!\n", \
__FILE__, __LINE__, __func__); \
} \
_taken = -ETIMEDOUT; \
} \
_taken; \
})
#define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond)
#define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond)
extern struct nvkm_oclass nv04_timer_oclass;
extern struct nvkm_oclass gk20a_timer_oclass;
int nv04_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
int nv40_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
int nv41_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
int gk20a_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
#endif
drivers/gpu/drm/nouveau/nouveau_abi16.c
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......@@ -13,9 +13,9 @@ int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
struct nouveau_abi16_ntfy {
struct nvif_object object;
struct list_head head;
struct nvkm_mm_node *node;
u32 handle;
};
struct nouveau_abi16_chan {
......@@ -37,7 +37,7 @@ struct nouveau_drm;
struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *, struct drm_device *);
int nouveau_abi16_put(struct nouveau_abi16 *, int);
void nouveau_abi16_fini(struct nouveau_abi16 *);
u16 nouveau_abi16_swclass(struct nouveau_drm *);
s32 nouveau_abi16_swclass(struct nouveau_drm *);
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
......
drivers/gpu/drm/nouveau/nouveau_acpi.c
View file @ 3439633a
......@@ -372,12 +372,12 @@ static int nouveau_rom_call(acpi_handle rom_handle, uint8_t *bios,
return len;
}
bool nouveau_acpi_rom_supported(struct pci_dev *pdev)
bool nouveau_acpi_rom_supported(struct device *dev)
{
acpi_status status;
acpi_handle dhandle, rom_handle;
dhandle = ACPI_HANDLE(&pdev->dev);
dhandle = ACPI_HANDLE(dev);
if (!dhandle)
return false;
......
drivers/gpu/drm/nouveau/nouveau_acpi.h
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