Commit 522b3d49 authored by Greg Ungerer's avatar Greg Ungerer

m68knommu: fix 5407 ColdFire UART vector setup

There is a couple of problems with the UART vector setup for the 5307
ColdFire UART. The ICR register access should be 8bit, not 32bit. The
address of the UIVR register is wrong, it needs to be offset into the
MBAR register region. Fix these.
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 9242ef12
...@@ -56,12 +56,12 @@ static struct platform_device *m5407_devices[] __initdata = { ...@@ -56,12 +56,12 @@ static struct platform_device *m5407_devices[] __initdata = {
static void __init m5407_uart_init_line(int line, int irq) static void __init m5407_uart_init_line(int line, int irq)
{ {
if (line == 0) { if (line == 0) {
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) { } else if (line == 1) {
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
} }
} }
......
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