Commit 5b4a1a8b authored by Shiraz Saleem's avatar Shiraz Saleem Committed by Doug Ledford

i40iw: Reinitialize IEQ on MTU change

On a netdev MTU change event, the iWARP
Exception Queue (IEQ) buffers may not be
sized properly to handle the new MTU.

Reinitialize the IEQ with new MTU size on MTU
change event.

Also, add define for the max ethernet frame size
field in IEQ QP context instead of the snd_mss
define which is for iWARP QPs' MSS field.
Signed-off-by: default avatarShiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 9381699e
...@@ -348,7 +348,10 @@ void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2pa ...@@ -348,7 +348,10 @@ void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2pa
u16 qs_handle; u16 qs_handle;
int i; int i;
vsi->mtu = l2params->mtu; if (vsi->mtu != l2params->mtu) {
vsi->mtu = l2params->mtu;
i40iw_reinitialize_ieq(dev);
}
i40iw_fill_qos_list(l2params->qs_handle_list); i40iw_fill_qos_list(l2params->qs_handle_list);
for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
......
...@@ -1107,6 +1107,9 @@ ...@@ -1107,6 +1107,9 @@
#define I40IWQPC_SNDMSS_SHIFT 16 #define I40IWQPC_SNDMSS_SHIFT 16
#define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT) #define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT)
#define I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT 16
#define I40IW_UDA_QPC_MAXFRAMESIZE_MASK (0x3fffUL << I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT)
#define I40IWQPC_VLANTAG_SHIFT 32 #define I40IWQPC_VLANTAG_SHIFT 32
#define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT) #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT)
......
...@@ -964,14 +964,29 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev) ...@@ -964,14 +964,29 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
info.pd_id = 2; info.pd_id = 2;
info.sq_size = 8192; info.sq_size = 8192;
info.rq_size = 8192; info.rq_size = 8192;
info.buf_size = 2048; info.buf_size = iwdev->vsi.mtu + VLAN_ETH_HLEN;
info.tx_buf_cnt = 16384; info.tx_buf_cnt = 4096;
status = i40iw_puda_create_rsrc(&iwdev->vsi, &info); status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
if (status) if (status)
i40iw_pr_err("ieq create fail\n"); i40iw_pr_err("ieq create fail\n");
return status; return status;
} }
/**
* i40iw_reinitialize_ieq - destroy and re-create ieq
* @dev: iwarp device
*/
void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev)
{
struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, false);
if (i40iw_initialize_ieq(iwdev)) {
iwdev->reset = true;
i40iw_request_reset(iwdev);
}
}
/** /**
* i40iw_hmc_setup - create hmc objects for the device * i40iw_hmc_setup - create hmc objects for the device
* @iwdev: iwarp device * @iwdev: iwarp device
......
...@@ -123,5 +123,6 @@ enum i40iw_status_code i40iw_allocate_virt_mem(struct i40iw_hw *hw, ...@@ -123,5 +123,6 @@ enum i40iw_status_code i40iw_allocate_virt_mem(struct i40iw_hw *hw,
enum i40iw_status_code i40iw_free_virt_mem(struct i40iw_hw *hw, enum i40iw_status_code i40iw_free_virt_mem(struct i40iw_hw *hw,
struct i40iw_virt_mem *mem); struct i40iw_virt_mem *mem);
u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq); u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq);
void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev);
#endif #endif
...@@ -488,7 +488,7 @@ static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc) ...@@ -488,7 +488,7 @@ static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc)
LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) | LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE)); LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE));
set_64bit_val(qp_ctx, 48, LS_64(1514, I40IWQPC_SNDMSS)); set_64bit_val(qp_ctx, 48, LS_64(rsrc->buf_size, I40IW_UDA_QPC_MAXFRAMESIZE));
set_64bit_val(qp_ctx, 56, 0); set_64bit_val(qp_ctx, 56, 0);
set_64bit_val(qp_ctx, 64, 1); set_64bit_val(qp_ctx, 64, 1);
......
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