Commit 6247cea2 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Kukjin Kim

ARM: SAMSUNG: Add support s3c2443-adc for S3C2443

The S3C2443-adc is 10 bit wide and has its mux-select
in an extra register at base+0x18
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent f8c414b5
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/fb-core.h> #include <plat/fb-core.h>
#include <plat/nand-core.h> #include <plat/nand-core.h>
#include <plat/adc-core.h>
static struct map_desc s3c2443_iodesc[] __initdata = { static struct map_desc s3c2443_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG), IODESC_ENT(WATCHDOG),
...@@ -70,6 +71,8 @@ int __init s3c2443_init(void) ...@@ -70,6 +71,8 @@ int __init s3c2443_init(void)
s3c_nand_setname("s3c2412-nand"); s3c_nand_setname("s3c2412-nand");
s3c_fb_setname("s3c2443-fb"); s3c_fb_setname("s3c2443-fb");
s3c_adc_setname("s3c2443-adc");
/* change WDT IRQ number */ /* change WDT IRQ number */
s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
......
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
enum s3c_cpu_type { enum s3c_cpu_type {
TYPE_ADCV1, /* S3C24XX */ TYPE_ADCV1, /* S3C24XX */
TYPE_ADCV11, /* S3C2443 */
TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
}; };
...@@ -106,6 +107,9 @@ static inline void s3c_adc_select(struct adc_device *adc, ...@@ -106,6 +107,9 @@ static inline void s3c_adc_select(struct adc_device *adc,
if (!client->is_ts) { if (!client->is_ts) {
if (cpu == TYPE_ADCV3) if (cpu == TYPE_ADCV3)
writel(client->channel & 0xf, adc->regs + S5P_ADCMUX); writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
else if (cpu == TYPE_ADCV11)
writel(client->channel & 0xf,
adc->regs + S3C2443_ADCMUX);
else else
con |= S3C2410_ADCCON_SELMUX(client->channel); con |= S3C2410_ADCCON_SELMUX(client->channel);
} }
...@@ -294,13 +298,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) ...@@ -294,13 +298,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
client->nr_samples--; client->nr_samples--;
if (cpu != TYPE_ADCV1) { if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
data0 &= 0x3ff;
data1 &= 0x3ff;
} else {
/* S3C64XX/S5P ADC resolution is 12-bit */ /* S3C64XX/S5P ADC resolution is 12-bit */
data0 &= 0xfff; data0 &= 0xfff;
data1 &= 0xfff; data1 &= 0xfff;
} else {
data0 &= 0x3ff;
data1 &= 0x3ff;
} }
if (client->convert_cb) if (client->convert_cb)
...@@ -321,7 +325,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) ...@@ -321,7 +325,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
} }
exit: exit:
if (cpu != TYPE_ADCV1) { if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
/* Clear ADC interrupt */ /* Clear ADC interrupt */
writel(0, adc->regs + S3C64XX_ADCCLRINT); writel(0, adc->regs + S3C64XX_ADCCLRINT);
} }
...@@ -492,6 +496,9 @@ static struct platform_device_id s3c_adc_driver_ids[] = { ...@@ -492,6 +496,9 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
{ {
.name = "s3c24xx-adc", .name = "s3c24xx-adc",
.driver_data = TYPE_ADCV1, .driver_data = TYPE_ADCV1,
}, {
.name = "s3c2443-adc",
.driver_data = TYPE_ADCV11,
}, { }, {
.name = "s3c64xx-adc", .name = "s3c64xx-adc",
.driver_data = TYPE_ADCV2, .driver_data = TYPE_ADCV2,
......
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