Commit 63d78cc9 authored by Russell King's avatar Russell King Committed by David S. Miller

net: mvpp2: set xlg flow control in mvpp2_mac_link_up()

Set the flow control settings in mvpp2_mac_link_up() for 10G links
just as we do for 1G and slower links. This is now the preferred
location.
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bd45f644
...@@ -4959,17 +4959,9 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, ...@@ -4959,17 +4959,9 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
{ {
u32 val; u32 val;
val = MVPP22_XLG_CTRL0_MAC_RESET_DIS;
if (state->pause & MLO_PAUSE_TX)
val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
if (state->pause & MLO_PAUSE_RX)
val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
MVPP22_XLG_CTRL0_MAC_RESET_DIS | MVPP22_XLG_CTRL0_MAC_RESET_DIS,
MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | MVPP22_XLG_CTRL0_MAC_RESET_DIS);
MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
MVPP22_XLG_CTRL4_EN_IDLE_CHECK | MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
...@@ -5159,10 +5151,17 @@ static void mvpp2_mac_link_up(struct phylink_config *config, ...@@ -5159,10 +5151,17 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
if (mvpp2_is_xlg(interface)) { if (mvpp2_is_xlg(interface)) {
if (!phylink_autoneg_inband(mode)) { if (!phylink_autoneg_inband(mode)) {
val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
if (tx_pause)
val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
if (rx_pause)
val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
MVPP22_XLG_CTRL0_FORCE_LINK_PASS, MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
MVPP22_XLG_CTRL0_FORCE_LINK_PASS); MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
} }
} else { } else {
if (!phylink_autoneg_inband(mode)) { if (!phylink_autoneg_inband(mode)) {
......
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