From 7f8232826842b27525857615262f50fe66c84dd7 Mon Sep 17 00:00:00 2001 From: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu, 7 Oct 2010 16:01:16 -0700 Subject: [PATCH] drm/i915: fix PCH eDP SSC support Enable SSC on PCH eDP if possible. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: added a posting read of PCH_DREF_CONTROL before the udelay] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5812fc7c5a0f..d7d59006a846 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3796,13 +3796,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, POSTING_READ(PCH_DREF_CONTROL); udelay(200); + } + temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; - temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; - temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; + /* Enable CPU source on CPU attached eDP */ + if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { + if (dev_priv->lvds_use_ssc) + temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; + else + temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; } else { - temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; + /* Enable SSC on PCH eDP if needed */ + if (dev_priv->lvds_use_ssc) { + DRM_ERROR("enabling SSC on PCH\n"); + temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; + } } I915_WRITE(PCH_DREF_CONTROL, temp); + POSTING_READ(PCH_DREF_CONTROL); + udelay(200); } } -- 2.30.9