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Commit 8ca1f3c0 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'sunxi-clk-for-5.7' of... 

Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Chen-Yu Tsai:

Changes consist mainly of cleanups for the display engine clock driver,
correcting clocks that don't exist. Also, the MBUS clock on the A64 is
exported for the device tree to consume.

* tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun8i-de2: Sort structures
  clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
  clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
  clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
  clk: sunxi-ng: sun8i-de2: Split out H5 definitions
  clk: sunxi-ng: a64: Export MBUS clock
parents bb6d3fb3 b998b75f
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Showing with 75 additions and 46 deletions
drivers/clk/sunxi-ng/ccu-sun50i-a64.h
View file @ 8ca1f3c0
......@@ -55,10 +55,6 @@
/* All the DRAM gates are exported */
/* Some more module clocks are exported */
#define CLK_MBUS 112
/* And the DSI and GPU module clock is exported */
#define CLK_NUMBER (CLK_GPU + 1)
......
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View file @ 8ca1f3c0
......@@ -50,8 +50,10 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_h6_de3_clks[] = {
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
&wb_clk.common,
......@@ -60,16 +62,16 @@ static struct ccu_common *sun50i_h6_de3_clks[] = {
&bus_mixer1_clk.common,
&bus_wb_clk.common,
&mixer0_div_clk.common,
&mixer1_div_clk.common,
&wb_div_clk.common,
&mixer0_div_a83_clk.common,
&mixer1_div_a83_clk.common,
&wb_div_a83_clk.common,
&bus_rot_clk.common,
&rot_clk.common,
&rot_div_clk.common,
&rot_div_a83_clk.common,
};
static struct ccu_common *sun8i_a83t_de2_clks[] = {
static struct ccu_common *sun8i_h3_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
&wb_clk.common,
......@@ -78,34 +80,38 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
&bus_mixer1_clk.common,
&bus_wb_clk.common,
&mixer0_div_a83_clk.common,
&mixer1_div_a83_clk.common,
&wb_div_a83_clk.common,
&mixer0_div_clk.common,
&mixer1_div_clk.common,
&wb_div_clk.common,
};
static struct ccu_common *sun8i_h3_de2_clks[] = {
static struct ccu_common *sun8i_v3s_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
&wb_clk.common,
&bus_mixer0_clk.common,
&bus_mixer1_clk.common,
&bus_wb_clk.common,
&mixer0_div_clk.common,
&mixer1_div_clk.common,
&wb_div_clk.common,
};
static struct ccu_common *sun8i_v3s_de2_clks[] = {
static struct ccu_common *sun50i_a64_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
&wb_clk.common,
&bus_mixer0_clk.common,
&bus_mixer1_clk.common,
&bus_wb_clk.common,
&mixer0_div_clk.common,
&mixer1_div_clk.common,
&wb_div_clk.common,
&bus_rot_clk.common,
&rot_clk.common,
&rot_div_clk.common,
};
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
......@@ -113,16 +119,19 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
[CLK_ROT] = &rot_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
[CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
},
.num = CLK_NUMBER_WITHOUT_ROT,
.num = CLK_NUMBER_WITH_ROT,
};
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
......@@ -156,7 +165,7 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.num = CLK_NUMBER_WITHOUT_ROT,
};
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
......@@ -179,9 +188,19 @@ static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* For A83T, H3 and R40, mixer1 reset line is shared with wb, so
* only RST_WB is exported here.
* For V3s there's just no mixer1, so it also shares this struct.
* Mixer1 reset line is shared with wb, so only RST_WB is
* exported here.
*/
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
* exported here.
* V3s doesn't have mixer1, so it also shares this struct.
*/
[RST_WB] = { 0x08, BIT(2) },
};
......@@ -190,13 +209,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
......@@ -215,28 +234,18 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.hw_clks = &sun8i_h3_de2_hw_clks,
.resets = sun8i_a83t_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
.resets = sun8i_h3_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun8i_h3_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
.hw_clks = &sun8i_h3_de2_hw_clks,
.hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
.ccu_clks = sun50i_h6_de3_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
.hw_clks = &sun50i_h6_de3_hw_clks,
.resets = sun50i_h6_de3_resets,
.num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
.resets = sun8i_a83t_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
......@@ -249,6 +258,26 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
.hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.ccu_clks = sun8i_h3_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
.hw_clks = &sun8i_h3_de2_hw_clks,
.resets = sun50i_h5_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
struct resource *res;
......@@ -337,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun8i-h3-de2-clk",
.data = &sun8i_h3_de2_clk_desc,
},
{
.compatible = "allwinner,sun8i-r40-de2-clk",
.data = &sun8i_r40_de2_clk_desc,
},
{
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = &sun8i_v3s_de2_clk_desc,
......@@ -347,11 +380,11 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = &sun50i_a64_de2_clk_desc,
.data = &sun50i_h5_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
.data = &sun50i_h6_de3_clk_desc,
.data = &sun50i_h5_de2_clk_desc,
},
{ }
};
......
include/dt-bindings/clock/sun50i-a64-ccu.h
View file @ 8ca1f3c0
......@@ -131,7 +131,7 @@
#define CLK_AVS 109
#define CLK_HDMI 110
#define CLK_HDMI_DDC 111
#define CLK_MBUS 112
#define CLK_DSI_DPHY 113
#define CLK_GPU 114
......
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