Commit 8f21d8d4 authored by Liu Ying's avatar Liu Ying Committed by Shawn Guo

ARM: imx6q: clk: Add the video_27m clock

This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 5f80e190
...@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) { if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
......
...@@ -248,6 +248,7 @@ ...@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS 235 #define IMX6QDL_PLL6_BYPASS 235
#define IMX6QDL_PLL7_BYPASS 236 #define IMX6QDL_PLL7_BYPASS 236
#define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_END 238 #define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_END 239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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